AM79C978 Advanced Micro Devices, AM79C978 Datasheet - Page 104
AM79C978
Manufacturer Part Number
AM79C978
Description
Single-Chip 1/10 Mbps PCI Home Networking Controller
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C978.pdf
(261 pages)
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PCI Status Register
Offset 06h
The PCI Status register is a 16-bit register that contains
status information for the PCI bus related events. It is
located at offset 06h in the PCI Configuration Space.
Bit
15
104
IOEN
Name
PERR
controller will only respond to ac-
cesses to the Expansion ROM
when both ROMEN (PCI Expan-
sion ROM Base Address register,
bit 0) and MEMEN are set to 1.
Since MEMEN also enables the
memory mapped access to the
Am79C978 I/O resources, the
PCI Memory Mapped I/O Base
Address register must be pro-
grammed with an address so that
the device does not claim cycles
not intended for it.
MEMEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
Am79C978 controller will ignore
all I/O accesses when IOEN is
cleared. The host must set IOEN
before the first I/O access to the
device. The PCI I/O Base Ad-
dress register must be pro-
grammed with a valid I/O address
before setting IOEN.
IOEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
the Am79C978 controller detects
a parity error.
The Am79C978 controller sam-
ples the AD[31:0], C/BE[3:0], and
the PAR lines for a parity error at
the following times:
• In slave mode, during the ad-
dress phase of any PCI bus com-
mand.
• In slave mode, for all I/O, mem-
ory, and configuration write com-
mands that select the Am79C978
controller when data is trans-
ferred (TRDY and IRDY are as-
serted).
I/O Space Access Enable. The
Description
Parity Error. PERR is set when
Am79C978
14
13
12
SERR
RMABORT Received Master Abort. RM-
RTABORT
• In master mode, during the data
phase of all memory read com-
mands.
In master mode, during the data
phase of the memory write com-
mand, the Am79C978 controller
sets the PERR bit if the target re-
ports a data parity error by as-
serting the PERR signal.
PERR is not effected by the state
of the Parity Error Response en-
able bit (PCI Command register,
bit 6).
PERR is set by the Am79C978
controller and cleared by writing a
1. Writing a 0 has no effect.
PERR is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
SERR is set by the Am79C978
controller and cleared by writing a
1. Writing a 0 has no effect.
SERR is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
RMABORT
Am79C978
cleared by writing a 1. Writing a 0
has no effect. RMABORT is
cleared by H_RESET and is not
affected by S_RESET or by set-
ting the STOP bit.
when the Am79C978 controller
detects an address parity error
and both SERREN and PERREN
(PCI Command register, bits 8
and 6) are set.
ABORT
Am79C978 controller terminates
a master cycle with a master
abort sequence.
ABORT is set when a target ter-
minates an Am79C978 master
cycle with a target abort se-
quence.
Signaled SERR. SERR is set
Received
is
Target
is
set
controller
set
Abort.
when
by
and
RT-
the
the
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