ISPGDX240VA-9B388I Lattice Semiconductor, ISPGDX240VA-9B388I Datasheet - Page 20

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ISPGDX240VA-9B388I

Manufacturer Part Number
ISPGDX240VA-9B388I
Description
In-System Programmable 3.3V Generic Digital CrosspointTM
Manufacturer
Lattice Semiconductor
Datasheet
The ispJTAG programming is accomplished by execut-
ing Lattice private instructions under the Boundary Scan
State Machine.
Details of the programming sequence are transparent to
the user and are handled by Lattice ISP Daisy Chain
Figure 11. Boundary Scan Register Circuit for Input-Only Pins
Figure 12. Boundary Scan State Machine
Boundary Scan (Continued)
0
1
Run-Test/Idle
Test-Logic-Reset
(from previous
Clock DR
0
SCANIN
Shift DR
Input Pin
cell
1
1
0
1
Select-DR-Scan
Capture-DR
Update-DR
Exit2-DR
Exit1-DR
Pause-DR
Shift-DR
0
0
0
1
1
1
0
20
Downlowad (ispDCD™), ispCODE ‘C’ routines or any
third-party programmers. Contact Lattice Technical Sup-
port to obtain more detailed programming information.
1
D
0
0
Specifications ispGDX240VA
1
Q
0
1
Select-IR-Scan
1
SCANOUT
(to next cell)
Capture-IR
Pause-IR
Update-IR
Exit1-IR
Shift-IR
Exit2-IR
0
0
1
0
1
1
0
1
0
0
1

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