AK4112 Asahi Kasei Microsystems, AK4112 Datasheet - Page 21

• Manufacturer Part Number: AK4112
• Description: High Feature 96kHz 24bit DIR
• Manufacturer: Asahi Kasei Microsystems

ASAHI KASEI
n n n n Serial Control Interface
The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO. The
data on this interface consists of Chip address (2bits, C0/1 are fixed to “00”), Read/Write (1bit), Register address (MSB
first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a
high-to-low transition of CSN. For read operations, the CDTO output goes high impedance after a low-to-high transition
of CSN. The maximum speed of CCLK is 5MHz. The CSN and CCLK must be fixed to “H” when the register does not
be accessed. PDN= “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4112A
should be reset by PDN= “L”.
MS0020-E-00
WRITE
READ
CCLK
CDTO
CDTO
CSN
CDTI
CDTI
C1
C1
0
C1-C0:
R/W:
A4-A0:
D7-D0:
C0
C0
1
R/W
R/W
Figure 10. Control I/F Timing
2
A4
A4
3
Chip Address (Fixed to “00”)
READ/WRITE (0:READ, 1:WRITE)
Register Address
Control Data
A3
A3
4
A2
- 21 -
A2
5
Hi-Z
Hi-Z
A1
A1
6
A0
A0
7
D7
D7
D7
8
D6
D6
D6
9
D5
D5
D5
10 11 12 13 14 15
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0
Hi-Z
[AK4112A]
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