AK4112 Asahi Kasei Microsystems, AK4112 Datasheet - Page 16

• Manufacturer Part Number: AK4112
• Description: High Feature 96kHz 24bit DIR
• Manufacturer: Asahi Kasei Microsystems

ASAHI KASEI
n Error Handling
There are the following five factors which ERF pin goes “H”. ERF pin shows the status of the internal PLL operation and
it is “L” when the PLL is OFF (Clock Operation Mode 1).
In Parallel Mode, ERF pin outputs the ORed signal including the factors of 1,2,3 and 4. Once ERF pin goes ”H”, it
maintains “H” for 1024/fs cycles after the all error factors are removed. Table 11 shows the state of each output pins
when the ERF pin is “H”. The Frame length Error is occurred when the interval of preamble in biphase signal is incorrect.
When unlock state, the channel status bits are not updated and the previous data is maintained.
In Serial Mode, ERF pin outputs the ORed signal including the factors of 1,2,3,4 and 5. However, Parity, Biphase and
Frame Length Error can be masked by MPAR bit, and the STC flag can be masked by MSTC bit. When those are masked
by each bit, the error factor does not affect ERF pin operation. The STC flag is set whenever a comparison between the
last sample of bits D5-0 of the receiver status 1 register (03H) and the new sample are different This comparison is made
every fs cycle. The STC flag is reset by reading the register 03H. This flag is also disabled during the first block after
reset.
Once ERF pin goes ”H”, it maintains “H” for 1024/fs cycles (can be changed by ERFH0-1 bits) after the all error factors
(In case of STC, from STC flag “1” to reading 03H) are removed. Once PAR, BIP, FRERR, V or UNLOCK bit goes “1”,
it returns “0” by reading Receiver Status 2 (04H). When unlock state, the channel status bits are not updated and the
previous data is maintained.
MS0020-E-00
Error
Unlock Error
Parity Error
Biphase Error
Frame Length Error
Status change
1. Unlock Error
2. Parity Error
3. Biphase Error
4. Frame length Error
5. STC (Status Change) flag=“1”
& Status
Error
Unlock Error
Parity Error
Biphase Error
Frame Length Error
UNLOCK
1
0
0
0
0
Table 12. Error handling (Serial Mode; MPAR=1, MSTC=1)
PAR
0
1
0
0
0
Table 11. Error handling (Parallel Mode)
: “H” when the PLL goes UNLOCK state.
: Updated every sub-frame cycle.
: Updated every sub-frame cycle
: Updated every sub-frame cycle
: Holds “1” until reading 03H.
Register
BIP
AUTO
Output
Output
Output
0
1
0
0
0
“L”
FRERR
0
0
0
1
0
- 16 -
Previous Data
Previous Data
Previous Data
SDTO
“L”
STC
0
0
0
0
1
AUTO
Output
Output
Output
Output
“L”
Output
Output
Output
“L”
V
Previous Data
Previous Data
Previous Data
Output
SDTO
“L”
Pin
Output
Output
Output
Output
“L”
V
[AK4112A]
Output
Output
Output
Output
Output
TX
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