AK7712 Asahi Kasei Microsystems, AK7712 Datasheet - Page 38

• Manufacturer Part Number: AK7712
• Description: Built-in 20-bit ADC/DAC Sophisticated Audio DSP
• Manufacturer: Asahi Kasei Microsystems

ASAHI KASEI
„ „ „ „ Accumulator(DR0 3)
Accumulator is a 34-bit register to store the result of calculation at ALU. 4 registers of DR0~3 can be used. The
choice of accumulator to input data is done at IDR field. The data of accumulator is output to DBUS and the A-input
of ALU, and it is possible to select the different accumulators for LDR and SCR at the same time. The
accumulator0(DR0) can output to DBUS and moreover can output the lower 24 bits in 2 ways as follows. One of
those is the intact lower 24 bits, and the other is the 24 bits which is changed upper 3 bits of lower 24 bits to "0". The
upper 13 bits of DR0 is connected to shifter directly. In the case of output to DBUS, the data judged overflow is also
output the intact 24-bit data when TDR* command is used.
„ „ „ „ Temporary Register(TMP0 7)
Temporary register is a 24-bit register to store the data of DBUS. The 8 registers of TMP0 7 are available. The
choice of temporary register to input the data is done at DST field, and to output the data to DBUS is done at SRC
field. The data transport of inter- temporary register (ex: TMP0 TMP3) can be also done through DBUS.
0180-E-02
IDR0 : Input result of ALU to DR0
IDR1 :
IDR2 :
IDR3 :
LDR0 : Output DR0 to the A input of ALU
LDR1 :
LDR2 :
LDR3 :
ODRB : Output the lower 24 bits of DR0 to DBUS
ODRL : Output the lower 24 bits of DR0 to DBUS
TMP0 : Output TMP0 to DBUS
TMP1 : Output TMP1 to DBUS
TMP2 : Output TMP2 to DBUS
TMP3 : Output TMP3 to DBUS
TMP4 : Output TMP4 to DBUS
TMP5 : Output TMP5 to DBUS
TMP6 : Output TMP6 to DBUS
TMP7 : Output TMP7 to DBUS
(upper 3 bits are "000")
DR1
DR2
DR3
DR1
DR2
DR3
<The List of Temporary Register Command>
<The List of Accumulator Command >
@TMP0 : Input the data of DBUS to TMP0
@TMP1 : Input the data of DBUS to TMP1
@TMP2 : Input the data of DBUS to TMP2
@TMP3 : Input the data of DBUS to TMP3
@TMP4 : Input the data of DBUS to TMP4
@TMP5 : Input the data of DBUS to TMP5
@TMP6 : Input the data of DBUS to TMP6
@TMP7 : Input the data of DBUS to TMP7
ODR0 : Output DR0 to DBUS with clip process
ODR1 :
ODR2 :
ODR3 :
TDR0 : Output DR0 to DBUS without clip process
TDR1 :
TDR2 :
TDR3 :
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DR1
DR2
DR3
DR1
DR2
DR3
[AK7712A-VT]
1997/12