AK7712 Asahi Kasei Microsystems, AK7712 Datasheet
AK7712
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AK7712 Summary of contents
Page 1
... ASAHI KASEI Built-in 20-bit ADC/DAC Sophisticated Audio DSP The AK7712A is a DSP(Digital Signal Processor) with built-in high performance 20bit 2ch ADC and 4ch DAC, on purposeto control the sound field possible to calculate 383 steps on 44.1kHz and 48kHz sampling respectively. In case of 32kHz sampling, it can caluculate up to 511 steps. With a combination of this LSI and external memory for delay data,it can berealized easily to control the sound field such as Echo, Surround Presence Controller, and Key-control which are needed forsomething like Karaoke ...
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... Division: 16-bit ALU: 34-bit arithmetic operation 24-bit arithmetic logic operation Shift: 1-,2-,3-,4-,6-,8-,15-bit right/left shift AK7712A has indirect shift function. (A shift using DBUS data can not use DBUS as multiplication input.) Register: 34-bit 24-bit Double precision operation: 24-bit(data)×31-bit(coefficient Internal Memory ...
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... ASAHI KASEI „ „ „ „ AK7712A Block Diagram 1) ADC,DAC Inside Connection Mode (OPCL: L) Note: Please use SDIN2,SDDA and SDDA2 with "L" or open. SDAD,SDOUT2 and SDOUT3 output "L". 0180-E-02 AK7712A Block Diagram - 3 - [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI 2) ADC,DAC Outside Connection Mode (built-in ADC,DAC isolation mode) (OPCL:H) 0180-E- [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI „ „ „ „ AK7712A DSP unit Block Diagram CP0,1 CRAM 256 16 128 CBUS (16-bit) DBUS (24-bit) MPX16 MPX24 X Y Multiply 24-bit 40-bit MUL DBUS SHIFT 34-bit 34-bit A B ALU 34-bit Overflow Margin:4bit DR0 3 24-bit Overflow Data Generator ...
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... ASAHI KASEI „ „ „ „ Ordering Guide AK7712A-VT -40 +85 C 100pin LQFP AKD7712A Evaluation Board „ „ „ „ Pin Layout 0180-E- [AK7712A-VT] 1997/12 ...
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... Address output for external RAM (A0:LSB justified, A16:MSB justified) O Write signal output for external SRAM/ Pseudo-SRAM/ DRAM O RAS for external DRAM / Pseudo-SRAM-CE O CAS for external DRAM / Pseudo-SRAM refresh I/O Data input/output for external RAM O Output enable signal output for external SRAM/ Pseudo-SRAM/ DRAM - 7 - [AK7712A-VT] 1997/12 ...
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... Output data ready output for microcomputer interface I Serial data input for microcomputer interface Serial data output for microcomputer interface (Hi-Z state at CS="H") Data write ready output for microcomputer interface (Hi-Z state at CS="H") I Chip select input for microcomputer interface - 8 - [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI „ „ „ „ AK7712A Control Signal, Input/Output Data Signal, Reset, etc. Pin No Pin name I/O 6 RST I Reset input ("L" Reset Power down 3 PDAD I AD reset control 4 PDDA I DA reset control 19 SDIN1 I Serial data input 1 MSB justified 16- 24-bit / LSB justified 16- 24-bit ...
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... Standard voltage input of ADC unit (normally connected to analog ground) I Standard voltage input of ADC unit (normally connected to 97 pin. 0.1u and 10uF capacitor are connected between this pin and VRADL pin.) O Common voltage (0.1u and 10uF capacitor are connected between this pin and analog ground [AK7712A-VT] 1997/12 ...
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... Test input 2 ; use as "L" or open Test input 3 ; use as "L" or open I ADC,DAC connection choice "L": connect , "H": separate I Zero point find set "H": DZF output , "L": DZF output "L" pins do not be bonded inside [AK7712A-VT] 1997/12 ...
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... Analog input/output voltages are proportional to the voltages of VRADH,VRDAH. * AKM assumes no responsibility for the usage beyond the conditions in this data sheet. 0180-E-02 Absolute Maximum Ratings Symbol VA (note IIN VINA (note 2) VIND Ta Tstg 6.0V. Recommended Operating Conditions Symbol min VA 4.75 VD 4. [AK7712A-VT] min max Unit -0.3 6.0 V -0.3 (VB)+0.3 V -0.3 6 -0.3 (VA)+0.3 V -0.3 (VB)+0 - ...
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... Aout(typ. @0dB) = 2.9Vpp × VRDAH/5 4: Between L channel and R channel of each DAC. 0180-E-02 Analog Characteristics min typ 105 0 1.9 2.0 220 (note 105 0 2.65 2. [AK7712A-VT] max Units 20 Bits 0.3 dB ppm 2.1 Vp Bits 0.5 dB ppm 3.15 Vp-p k 1997/12 ...
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... Digital Filter Characteristics Symbol min typ 24. 29.3 Symbol min 22. 14.7 - ±0 [AK7712A-VT] max Units 20.00 kHz 22.05 kHz kHz dB ±0.005 typ max Units 20.0 kHz - kHz kHz dB ±0. 1997/12 ...
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... This is the value in the conditions that external clock(XTI,BCLK,LRCK) is "L", SCLK is "H". 0180-E-02 DC Characteristics Symbol min typ VIH 70%VDD - VIL - - VOH VDD-0.1 - VOL - - Iin - - Iid - 100 min typ 47 51 (note 3) 20 490 0 [AK7712A-VT] max Units - V 30%VDD 0 max Units 250 uA 750 mW 1.25 mW 1997/12 ...
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... CLKH f 1.024 BLK SLK t 30 SLKL t 30 SLKH RST (note (note [AK7712A-VT] typ max Units 11.2896 12.288 MHz 16.9344 18.432 MHz 16.384 18.432 MHz 11.2986 12.288 MHz ns ns 16.9344 18.432 MHz ns ns 16.384 18.432 MHz ...
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... WRS t 100 WSC t 166(note1) SCW t 200 SLK t 80 SLKL t 80 SLKH t 50 SIH t 50 SIS t CSHR (note2) t CSHS t CSDR (note2) t SOS - 17 - [AK7712A-VT] typ max Units 30+t ns BLKL 64fs typ max Units ...
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... RSC 180 200 AHW t 95 105 ASW [AK7712A-VT] 12.288 Units min max 18 - 110 ns 170 135 12.288 Units min max 210 ns 135 ns 160 12.288 ...
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... SUCA HCLCA HWCH HCLW SUD HWLD WCH WCL - 19 - [AK7712A-VT] 12.288 Units min max 18 - 110 ns 170 135 135 160 12.288 Units min max 360 ns 170 ns 170 ...
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... ASAHI KASEI „ „ „ „ Timing Waveform 0180-E- [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI 0180-E- [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI 0180-E- [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI Read/Write Interface Timing of Pseudo SRAM (Static Column Mode) 0180-E- [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI 0180-E- [AK7712A-VT] 1997/12 ...
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... Each Blocks(PRAM,DRAM,CRAM,Calculation unit,etc.) actions on pipeline. On controlling of this pipeline, each stages(command fetch, command decode and execution) are handled in parallel, The operations for each block is executed by 32-bit holizontal code. Therefore each operations are executed equivalently in one machine cycle. The following is the executing timing of each command. 0180-E-02 Function Manual - 25 - [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI „ „ „ „ Calculation Function 1) Arithmetic System 0180-E- [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI << DBUS register,etc. >> Except for @IORL, take data from MSB. 0180-E- [AK7712A-VT] 1997/12 ...
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... Multiplication actions always synchronous with CMCK, the product is output in 2 cycles. 0180-E-02 -1. The following combinations are possible for input. 24-bit Input notes Data RAM DBUS Data RAM 2 DBUS calculation of X 16-bit 24-bit Input Register X Y Partial Product Partial Product Register Carry Sum Final Adder 40-bit Shifter - 28 - [AK7712A-VT] 1997/12 ...
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... The obtained value X YH should be added after shifting 16 bits to left compared with X YL. But the data which is shifted 1bit to right, actually added after shifting 15 bits to left. ,OP, , ,OP, , ,OP, ,OP, ,OP, ,IDR0=SH0 << ,OP, ,IDR0=SHRF + LDR0 0180-E-02 <Example of Calculation Program (24 ,CPU,DU1,,, ;Read of Coefficient(MSB) and Data ,CPU, ,,, ;Read of Coefficient(LSB ,,, , , ,,, , , ,,, , , ,,, ;(X YH) + 15-bit right-shifted (X YL [AK7712A-VT] 31-bit)> 1997/12 ...
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... LDR0 ,PP, ,IDR0=BHRF + LDR0 ,OP, , ,PP, ,IDR1=BDRF + LDR1 0180-E-02 31-bit)> ,CPU,DU1,, ,;Read of Coefficient(MSB) and Data(MSB ,DU1,, ,;YH XH,Read of Data(LSB) ,CPU, ,, ,;YH XH,Read of Coefficient(LSB) , ,DD1,, ,;YH XL(shifted 6bit to right ,;YL XL(shifted 21 to right ,; ,,ODR2 ,; , , ,, ,;ODRB: lower 24 bits data , , ,,ODRB ,;DR1: upper 24 bits data - 30 - [AK7712A-VT] 1997/12 ...
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... In this way, upper 24 bits and lower 21 bits are calculated. <Example of Calculation Program(45 ,OP, , ,OP, , ,OP, ,OP, ,OP,CR DR ,IDR0=SDLF << ,OP, ,IDR1=SH0 << ,OP, ,IDR0=SHR6 + LDR0 ,OP, , ,PP, ,IDR1=BDRF + LDR1 0180-E-02 16-bit)> ,CPU,DU1,, , ;Read of Coefficient(MSB), Data(MSB ,CPU XH,Read of Coefficient(LSB XL(shifted 6bit to right ;ODRB: lower 24 bits data , , ,,ODRB, ;DR1: upper 24 bits data - 31 - [AK7712A-VT] 1997/12 ...
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... DBUS data, you can use only CRAM and DRAM data for multiplication input at the same line. The indirect shift command is carried out in 1 step, taking priority of shift field command. The Timing of shift command is showed below. 0180-E- [AK7712A-VT] 1997/12 ...
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... The example of program is shown as follows. (assuming that DR0 is regulated.) ,OP,, ,,,,ODR0 ,@PDR ;detecting size of DR0 ,OP,, ,,,,PDR ,PP,,IDR0=BH0 << ,,,,ODR0 , 0180-E- lower 6 bits ="0" <Example of Data Regulating> ,@SHR ;setting shift number with indirect shift ;execution of indirect shift taking priority of BH0 after 1 step [AK7712A-VT] 1997/12 ...
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... DBUS data shifted 4 bits to left *BHL6: the DBUS data shifted 6 bits to left *BHL8: the DBUS data shifted 8 bits to left *BHLF: the DBUS data shifted 15 bits to left *#BDRF: the DBUS data shifted 15 bits to left 31 [AK7712A-VT] Shift no shift 1 bit to right 2 bits to right 3 bits to right 4 bits to right ...
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... In the case that the calculated data is output on DBUS, the data is rounded off to 24bits. <Example program for 24-bit data output> ,OP,CR*DR, ,OP,CR*DR, ,OP,CR*DR,IDR0=SH0 <1 ,OP, ,IDR0=SH0 + LDR0 ,,,, ,OP, ,IDR0=SH0 + LDR0 ,,,, ,OP, , ,OP, , 0180-E-02 * 24-bit arithmetic logical operation $ : OR & : AND # : Exclusive- NOT A+1 negative overflow: 800000(HEX). ,,,, , ; ,,,, , ; ,,,, , ; , ; , ; ,,,, , ; ,,,,ODR0, ;ODR0 is the rounded value of calculated data - 35 - [AK7712A-VT] 1997/12 ...
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... RE B × { × × { × × { × RE all "0" [AK7712A-VT] ALU function + + + + + + positive: + negative: invertion + AND EXOR NOT 1997/12 ...
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... This circuitry renews the data at every sampling cycle and output data is connected to DBUS result, the value for 24bit can be asked at the sampling cycle when MRSG are pointed out in the DST field. Besides, in case of use of pink noise generator circuitry, C5 should be set to 1 when control resistors are set. 0180-E- [AK7712A-VT] 1997/12 ...
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... Input the data of DBUS to TMP1 @TMP2 : Input the data of DBUS to TMP2 @TMP3 : Input the data of DBUS to TMP3 @TMP4 : Input the data of DBUS to TMP4 @TMP5 : Input the data of DBUS to TMP5 @TMP6 : Input the data of DBUS to TMP6 @TMP7 : Input the data of DBUS to TMP7 - 38 - [AK7712A-VT] 1997/12 ...
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... CP0, CP1+1) ;be able to output to DBUS and multiplier(CR) 2 steps after ; ; ;output the data written 1step before by @CRAM to CR and DBUS ; ; ;output the data of pointer changed 2 steps before by CRC ;operate with the changed pointer until next CPC is executed - 39 - [AK7712A-VT] CP1 and increment of 1997/12 ...
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... DD3: address-3 DRAM: output the data to DBUS(at the same time to selector of multiplier) @DP0: load the DBUS data to DRAM-CP0 pointer @DP1: load DBUS data to DRAM-CP1 pointer @DRAM: write DBUS data 0180-E-02 ). The starting pointer appointment for every sampling cycle is chosen [AK7712A-VT] 1997/12 ...
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... DBUS and multiplier(DR) 2 steps after ;write the data written 1 step before by @DRAM to DR and DBUS ;output the data of pointer changed 2 steps before by DPC. ;operation with changed pointer until the next DPC is executed + sampling frequency after RUN + sampling frequency after RUN - 41 - [AK7712A-VT] ) with ring 1997/12 ...
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... ASAHI KASEI 0180-E- [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI 0180-E- [AK7712A-VT] 1997/12 ...
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... 00000001********/11111110******** 000000001*******/111111110******* 0000000001******/1111111110****** 00000000001*****/11111111110***** 000000000001****/111111111110**** 0000000000001***/1111111111110*** 00000000000001**/11111111111110** 000000000000001*/111111111111110* 0000000000000001/1111111111111110 0000000000000000/1111111111111111 0180-E-02 input data transformed value 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 - 44 - [AK7712A-VT] 1997/12 ...
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... The timing of each instructions are shown below. , Jump The timing of jump is shown in the figure below. As the figure shows, 1 machine cycle of NOP is inserted before jumping from the address of jump command to appointed address. 0180-E- [AK7712A-VT] 1997/12 ...
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... And not satisfied then NOP is not inserted, and next address command is executed. The list of conditional jump is shown below. JLE : SGF=1 or ZRF=1 JLS : JGE : JGR : SGF=0 and ZRF=0 JZR : JNZ : JOV : JNO : 0180-E-02 <List of Conditional Jump Command> condition ALU(A- SGF < SGF > B ZRF ZRF=0 OVF=1 OVF [AK7712A-VT] 1997/12 ...
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... The timing of subroutine call is shown as follows. This command stacks next address before address of call destination, NOP is inserted. The preparation for pushing the stacked address is done on return address, and stack address is executed after return address. Then NOP is not inserted. 0180-E- [AK7712A-VT] 1997/12 ...
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... The timing of load command is shown in the figure below. This command loads the data to objective register through the BUS inter-connection and DBUS. , End Command (ED) The timing of end command is shown in the figure below. This command inserts NOP until the rising edge of LRCK. 0180-E- [AK7712A-VT] 1997/12 ...
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... The timing of loop command is shown in the figure below. This command operates the programs from next command of the appointed sequence command for loop to the address appointed to return register loop times(maximum 31(1Fh) times) over. NOP is not inserted at each the return. 0180-E- [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI „ „ „ „ Input/Output Function DSP unit of AK7712A has 4 channels of digital input port and 6 channels of digital output port. 2 channels of input ports (SDIN2) can be connected to internal ADC, 2 channels of output ports (SDOUT2) can be connected to internal DAC1. And another 2 channels of output ports(SDOUT3) can be connected to internal DAC2. The command related to these above is as follows ...
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... Control Register setting C17, C16 16bit MSB justified 24bit MSB justified 16bit LSB justified 0180-E-02 C15, C14 Fig.7 SDIN1 Master Mode Input Format C13, C12 Fig.8 SDOUT1 Master Mode Output Format - 51 - [AK7712A-VT] 1997/12 ...
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... Fig.9 SDIN1 Slave Mode Input Format ( SDOUT1 ( Output ) Control Register setting C17, C16 16bit MSB justified 24bit MSB justified 16bit LSB justified Fig.10 SDOUT1 Slave Mode Output Format ( 64fs ) 0180-E-02 C15, C14 C13, C12 [AK7712A-VT] 1997/12 ...
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... Fig.11 SDIN1 Slave Mode Input Format ( SDOUT1 ( Output ) Control Register setting C17, C16 16bit MSB justified 24bit MSB justified 16bit LSB justified Fig.12 SDOUT1 Slave Mode Output Format ( 48fs ) 0180-E-02 C15, C14 C13, C12 [AK7712A-VT] 1997/12 ...
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... Control Register setting C17, C16 16bit MSB justified Fig.13 SDIN1 Slave Mode Input Format ( SDOUT1 ( Output ) Control Register setting C17, C16 16bit MSB justified Fig.14 SDOUT1 Slave Mode Output Format ( 32fs ) 0180-E-02 C15, C14 C13, C12 [AK7712A-VT] 1997/12 ...
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... SDIN2 1) Master Mode ( 64fs ) SDAD ( Output ) 20bit MSB justified SDIN2 ( Input ) Control Register setting C17, C16 20bit MSB justified 16bit MSB justified 0180-E-02 Fig.15 SDAD Master Mode Output Format C11 0 1 Fig.16 SDIN2 Master Mode Input Format - 55 - [AK7712A-VT] 1997/12 ...
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... Slave Mode [64fs] SDAD ( Output ) 20bit MSB justified Fig.17 SDAD Slave Mode Output Format ( 64fs ) SDIN2 ( Input ) Control Register setting C17, C16 20bit MSB justified 16bit MSB justified Fig.18 SDIN2 Slave Mode Input Format ( 64fs ) 0180-E-02 C11 [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI [48fs] SDAD ( Output ) 20bit MSB justified Fig.19 SDAD Slave Mode Output Format ( 48fs ) SDIN2 ( Input ) Control Register setting C17, C16 20bit MSB justified 16bit MSB justified Fig.20 SDIN2 Slave Mode Input Format ( 48fs ) 0180-E-02 C11 [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI [32fs] SDAD ( Output ) 16bit MSB justified Fig.21 SDAD Slave Mode Output Format ( 32fs ) SDIN2 ( Input ) Control Register setting C17, C16 16bit MSB justified Fig.22 SDIN2 Slave Mode Input Format ( 32fs ) 0810-E-02 C11 [AK7712A-VT] 1997/12 ...
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... Control Register setting C17, C16 20bit MSB justified 16bit MSB justified SDDA ( Input ) Control Register setting C17, C16 20bit MSB justified 0810-E-02 C10 0 1 Fig.23 SDOUT2 Master Mode Output Format Fig.24 SDDA Master Mode Input Format - 59 - [AK7712A-VT] 1997/12 ...
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... Control Register setting C17, C16 20bit MSB justified 16bit MSB justified Fig.25 SDOUT2 Slave Mode Output Format ( 64fs ) SDDA ( Input ) Control Register setting C17, C16 20bit MSB justified Fig.26 SDDA Slave Mode Input Format ( 64fs ) 0810-E-02 C10 [AK7712A-VT] 1997/12 ...
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... Control Register setting C17, C16 20bit MSB justified 16bit MSB justified Fig.27 SDOUT2 Slave Mode Output Format ( 48fs ) SDDA ( Input ) Control Register setting C17, C16 20bit MSB justified Fig.28 SDDA Slave Mode Input Format ( 48fs ) 0810-E-02 C10 [AK7712A-VT] 1997/12 ...
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... SDOUT2 ( Output ) Control Register setting C17, C16 16bit MSB justified Fig.29 SDOUT2 Slave Mode Output Format ( 32fs ) SDDA ( Input ) Control Register setting C17, C16 20bit MSB justified Fig.30 SDDA Slave Mode Input Format ( 32fs ) 0810-E-02 C10 [AK7712A-VT] 1997/12 ...
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... SDDA2 1) Master Mode ( 64fs ) SDOUT3 ( Output ) Control Register setting C17, C16 20bit MSB justified Fig.31 SDOUT3 Master Mode Output Format SDDA2 ( Input ) Control Register setting C17, C16 20bit MSB justified 0810-E-02 Fig.32 SDDA2 Master Mode Input Format - 63 - [AK7712A-VT] 1997/12 ...
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... Slave Mode ( 64fs ) [64fs] SDOUT3 ( Output ) Control Register setting C17, C16 20bit MSB justified Fig.33 SDOUT3 Slave Mode Output Format ( 64fs ) SDDA2 ( Input ) Control Register setting C17, C16 20bit MSB justified Fig.34 SDDA2 Slave Mode Input Format ( 64fs ) 0810-E- [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI [48fs] SDOUT3 ( Output ) Control Register setting C17, C16 20bit MSB justified Fig.35 SDOUT3 Slave Mode Output Format ( 48fs ) SDDA2 ( Input ) Control Register setting C17, C16 20bit MSB justified Fig.36 SDDA2 Slave Mode Input Format ( 48fs ) 0810-E- [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI [32fs] SDOUT3 ( Output ) Control Register setting C17, C16 16bit MSB justified Fig.37 SDOUT3 Slave Mode Output Format ( 32fs ) SDDA2 ( Input ) Control Register setting C17, C16 16bit MSB justified Fig.38 SDDA2 Slave Mode Input Format ( 32fs ) 0810-E- [AK7712A-VT] 1997/12 ...
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... Transfer Procedure> A8) (A7 A0) (D31 D24) (D23 D16) (D15 D8) (D7 D0) <Data Transfer Procedure> (A7 A0) (D15 D8) (D7 D0 [AK7712A-VT] 1997/12 ...
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... Transfer Procedure> command code ( data (D15 data (D7 command code:CRAM ( :OFRAM ( first address ( [AK7712A-VT] A0) D8) D0 D8) D0) A0) 1997/12 ...
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... The register, which is controlling the action mode of this LSI, is consists of 24 bits. The function of each bit is shown in Table 1 as follows. 0180-E-02 < Data Transfer Procedure> (D7 D0) <Data Transfer Procedure> (C23 C16) (C15 C8) (C7 C0 [AK7712A-VT] 1997/12 ...
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... DSP fs Max clock 384fs 48/44.1/32kHz 18.432MHz 256 48/44.1/32 12.288MHz 512 32 16.384MHz 576 32 18.432MHz 0: (default value) 0: (default value [AK7712A-VT] 32/48/64fs 48/64fs 48/64fs 64fs 32/48/64fs 48/64fs 48/64fs 48/64fs 32/48/64fs 48/64fs 32/48/64fs note 1) note 1) 1: use note 1) note 1) note 1) 1997/12 ...
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... The motion transferring next data is suppressed in that period(WRDY= "L"). Since the period has short length about 2 cycles of master clock, if SCLK is slow enough then monitoring of WRDY is not needed. Fig.38 Input of Continuos Address Data to PRAM,CRAM and OFRAM Fig.39 Input of Discontinuos Address Data to PRAM,CRAM and OFRAM 0180-E- [AK7712A-VT] 1997/12 ...
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... WRQ to "L" and if input of command code and address is finished then set WRQ to "H". If the preparation for rewrite is finished inside, WRDY signal becomes "L", and rewrite command is executed from rising of LRCK. And if rewriting is finished, WRDY becomes to "H". These timing is shown in Fig.41. 0180-E-02 Fig.41 Data Rewrite Timing at Run State - 72 - [AK7712A-VT] 1997/12 ...
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... RST/WRQ to "H", becomes "L" "H" at rising edge of LRCK. As similar to above, data transferring is suppressed in the period of WRDY="L". Fig.42 Write Timing External Conditional Jump at Reset Fig.43 Write Timing of External Conditional Jump at Run time 0180-E- [AK7712A-VT] 1997/12 ...
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... "H" state. „ High-pass Filter AK7712A has digital high-pass filter(HPF) for DC offset cancel. HPF is active when control register C6 is "0". The cut-off frequency of HPF is about 1Hz(fs=48kHz set to "1" then HPF becomes unavailable. In that case, AK7712A has DC offset of a few millivolts. „ ...
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... ASAHI KASEI „ System Clock The system clock of AK7712A is XTI at master mode. And these are XTI, LRCK(fs) and BCLK at slave mode. In case of using slave mode, XTI and LRCK must be synchronized but those phases do not need to be muched. Master clock can be obtained by quartz oscillator ...
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... LRCK. So, change clock with RST "L"(PDAD,PDDA="L"), and reset both built-in ADC,DAC. But, the phase shift between LRCK and inside timing is out of the range from 1/16 to -1/16 of input sampling cycle(1/fs), the adjustment of phase of inside timing is done synchronized with LRCK" "(same as reset state). 0180-E- [AK7712A-VT] 1997/12 ...
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... RUN RUN Õ: can not run [AK7712A-VT] The format is shown in the table . In the case of writing data to control register, set PDAD and PDDA to "L". To make the change of PDAD and PDDA, set RST to "L". 1997/12 ...
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... If both of RST and PD are set to "L", this LSI becomes power down state, so the control register is also reset to default state. After cancellation, it actions same above. To change the control register or program, set PD to "H", load data, set RST to "H". Fig.46 Timing at Power Down and after Cancellation of Reset 0180-E- [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI Connection : 0180-E-02 System Design - 79 - [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI The connection to external RAM is as follows. 0180-E- [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI <Pseudo SRAM> 0180-E- [AK7712A-VT] 1997/12 ...
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... VRADH pin and VRADL pin. Since the analog power supply voltage of AK7712A is set to +5V, do not input the voltage more than (AVDD1)+0.3V or the voltage less than (AVSS1)-0.3V or the current more than 10mA to analog input pin(AINL,AINR). The over current causes destruction of inner protective circuit, moreover latch-up, and the IC falls into destruction ...
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... Fig.47 Example of Input Buffer Circuit(Differential Input) Fig.48 Example of Input Buffer Circuit(Single-end Input also available to input analog signal to AK7712A with single-end. In that case, input the analog signal(in case of usingthe inner standard voltage, the full-scale is 4.0Vp-p) to AIN-input, and input the bias to AIN+input. But, at using single-end input type, 2nd harmonic distortion is pretty big, then the features of S/N+D will be worse than at using differential input (Fig ...
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... In this example, output is reversed. 5. Connection with Digital Circuit To minimize the noise caused by digital circuit, connect CMOS logic to digital output. The conformable logic families are 4000B, 74HC, 74AC, 74ACT and 74HCT. 0180-E-02 Fig.49 Example of External Circuit(Gain [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI „ 100pin LQFP (Unit: mm) „ „ „ „ Material & Lead finish Package: Epoxy Lead-frame: Copper Lead-finish: Soldering plate 0180-E-02 Package - 85 - [AK7712A-VT] 1997/12 ...
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... ASAHI KASEI XXXXAAA Data Code Identifier XXXX: Assembly Date (number) AAA: Lot Number (alphabet) 0180-E-02 Marking - 86 - [AK7712A-VT] 1997/12 ...
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... IMPORTANT NOTICE These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein ...