AS7C256A ETC, AS7C256A Datasheet - Page 2

• Manufacturer Part Number: AS7C256A
• Description: 5V/3.3V 32K X 8 CMOS SRAM (Common I/O)
• Manufacturer: ETC

Functional description
The AS7C(3)256A is a 5V/3.3V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized
as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including Pentium
PowerPC
sacrificing performance or operating margins.
The device enters standby mode when
reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode. Both versions of
the AS7C256A offer 2.0V data retention.
Equal address access and cycle times (t
ideal for high-performance applications. The chip enable (
memory organizations.
A write cycle is accomplished by asserting chip enable (
written on the rising edge of
O pins only after outputs have been disabled with
A read cycle is accomplished by asserting chip enable (
drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable
is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible and 5V tolerant. Operation is from a single 3.3±0.3V supply. The AS7C(3)256A
is packaged in high volume industry standard packages.
Absolute maximum ratings
Parameter
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Truth table
CE
Key:
Voltage on V
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with V
DC current into outputs (low)
H
L
L
L
3/7/01; V.0.9.2
X = Don’t care, L = Low, H = High
TM
, and portable computing. Alliance’s advanced circuit design and process techniques permit 3.3V operation without
CC
relative to GND
WE
X
H
H
L
CC
WE
applied
(write cycle 1) or
CE
AA
is high. CMOS standby mode consumes 3.6 mW . Normal operation offers 75% power
OE
X
H
L
X
, t
Device
AS7C256A
AS7C3256A
RC
, t
WC
Alliance Semiconductor
) of 10/12/15/20 ns with output enable access times (t
output enable (
CE
(write cycle 2). To avoid bus contention, external devices should drive I/
CE
CE
) and output enable (
) and write enable (
Data
High Z
High Z
D
D
OUT
IN
CE
OE
Symbol
V
V
V
P
T
T
I
OUT
) input permits easy memory expansion with multiple-bank
D
) or write enable
stg
bias
t1
t1
t2
®
Min
–0.5
–0.5
–0.5
–
–65
–55
–
(
OE
WE
WE
) LOW , with write enable (
).
) LOW . Data on the input pins I/O0-I/O7 is
Mode
Standby (I
Output disable (I
Read (I
Write (I
Max
+7.0
+5.0
V
1.0
+150
+125
20
CC
+ 0.5
CC
CC
)
SB
)
, I
OE
SB1
) of 3/3/4/5 ns are
WE
CC
)
AS7C3256A
) high. The chip
AS7C256A
)
Unit
V
V
V
W
o
o
mA
C
C
P. 2 of 8
TM
,