GAL16VP8B-15LJ Lattice Semiconductor, GAL16VP8B-15LJ Datasheet - Page 4

• Manufacturer Part Number: GAL16VP8B-15LJ
• Description: High-Speed E2CMOS PLD Generic Array Logic
• Manufacturer: Lattice Semiconductor

In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/Os are possible in this mode.
Dedicated input or output functions can be implemented as sub-
sets of the I/O function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
Registered Mode
OE
CLK
XOR
XOR
D
Q
Q
4
Registered outputs have eight product terms per output. I/Os have
seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signa-
ture (UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the following page.
Registered Configuration for Registered Mode
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 1 controls common CLK for the registered outputs.
- Pin 10 controls common OE for the registered outputs.
- Pin 1 & Pin 10 are permanently configured as CLK & OE
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 1 & Pin 10 are permanently configured as CLK & OE
for registered output configuration.
for registered output configuration.
Specifications GAL16VP8