ispPAC-CLK55xx Lattice Semiconductor, ispPAC-CLK55xx Datasheet - Page 20

• Manufacturer Part Number: ispPAC-CLK55xx
• Description: In-System Programmable Clock Generator with Universal Fan-Out Buffer
• Manufacturer: Lattice Semiconductor

Lattice Semiconductor
ispClock5500 Family Data Sheet
LVDS/Differential LVPECL
The receiver should be set to LVDS or LVPECL mode as required and both termination resistors should be
engaged and set to 50Ω. The REFVTT pin, however, should be left unconnected. This creates a floating 100Ω dif-
ferential termination resistance across the input terminals. The LVDS termination configuration is shown in
Figure 16.
Figure 16. LVDS Input Receiver Configuration
ispClock5500
Differential
+Signal In
Receiver
REFA+
LVDS
Driver
-Signal In
REFA-
50
50
CLOSED
CLOSED
No Connect
REFVTT
Note that while a floating 100Ω resistor forms a complete termination for an LVDS signal line, additional circuitry
may be required to satisfactorily terminate a differential LVPECL signal. This is because a true bipolar LVPECL out-
put driver typically requires an external DC ‘pull-down’ path to a V
termination voltage (typically VCC-2V) to
TERM
properly bias its open emitter output stage. When interfacing to an LVPECL input signal, the ispClock5500’s inter-
nal termination resistors should not be used for this pull-down function, as they may be damaged from excessive
current. The pull-down should be implemented with external resistors placed close to the LVPECL driver
(Figure 17)
Figure 17. LVPECL Input Receiver Configuration
ispClock5500
Differential
+Signal In
Receiver
REFA+
LVPECL
Driver
-Signal In
REFA-
R
R
50
50
PD
PD
CLOSED
CLOSED
V
No Connect
TERM
REFVTT
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