UPSD3233 STMicroelectronics, UPSD3233 Datasheet - Page 32
UPSD3233
Manufacturer Part Number
UPSD3233
Description
Flash Programmable System Devices with 8032 Microcontroller Core
Manufacturer
STMicroelectronics
Datasheet
1.UPSD3233.pdf
(175 pages)
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UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
UPSD3200 HARDWARE DESCRIPTION
The uPSD323X Devices has a modular architec-
ture with two main functional modules: the MCU
Module and the PSD Module. The MCU Module
consists of a standard 8032 core, peripherals and
other system supporting functions. The PSD Mod-
ule provides configurable Program and Data mem-
ories to the 8032 CPU core. In addition, it has its
own set of I/O ports and a PLD with 16 macrocells
for general logic implementation. Ports A,B,C, and
D are general purpose programmable I/O ports
Figure 15. uPSD323X Devices Functional Modules
32/175
Intr, Timers,I 2 C
Port 3, UART,
2 UARTs
Interrupt
PSD MODULE
Port 3
MCU MODULE
8032 Core
Page Register
Decode PLD
256 Byte SRAM
Counters
JTAG ISP
3 Timer /
Port 1
JTAG, PLD I/O
2nd UART and ADC
Port 1, Timers and
and GPIO
I2C
Port C,
1Mb or 2Mb
Main Flash
Channel
CPLD - 16 MACROCELLS
ADC
4
8032 Internal Bus
PSD Internal Bus
Port A & B, PLD
I/O and GPIO
Secondary
256Kb
Flash
Channels
PWM
5
that have a port architecture which is different from
Ports 0-4 in the MCU Module.
The PSD Module communicates with the CPU
Core through the internal address, data bus (A0-
A15, D0-D7) and control signals (RD_, WR_,
PSEN_ , ALE, RESET_). The user defines the De-
coding PLD in the PSDsoft Development Tool and
can map the resources in the PSD Module to any
program or data address space.
Port 4 PWM
and DDC
w/ 256 Byte
Port D
GPIO
SRAM
64Kb
SRAM
DDC
RD,PSEN
WR,ALE
A0-A15
Transceiver
Interface
Dedicated
USB Pins
USB
Bus
&
VCC, GND,
D0-D7
Dedicated
XTAL
Pins
LVD & WDT
Reset Logic
Reset
AI06619C
Port 0, 2
Ext. Bus