M306V5EESP Mitsubishi, M306V5EESP Datasheet - Page 105

• Manufacturer Part Number: M306V5EESP
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
• Manufacturer: Mitsubishi

Rev. 1.0
2.11.3 Clock Asynchronous Serial I/O (UART) Mode
Table 2.11.5 Specifications of UART Mode (1)
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 2.11.5 and 2.11.6 list the specifications of the UART mode. Figure 2.11.21 and
2.11.22 show the UARTi transmit/receive mode register in UART mode.
Transfer data format
Transfer clock
Transmission start condition • To start transmission, the following requirements must be met:
Reception start condition
Interrupt request
generation timing
Error detection
Item
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
• When internal clock is selected (bit 3 at addresses 03A0
• When external clock is selected (bit 3 at addresses 03A0
- Transmit enable bit (bit 0 at addresses 03A5
- Transmit buffer empty flag (bit 1 at addresses 03A5
• To start reception, the following requirements must be met:
• When transmitting
-
- Transmit interrupt cause select bits (bits 0 at address 03B0
•
- Interrupts requested when data transfer from UARTi receive register to
• Overrun error (Note 3)
• Framing error
• Parity error
• Error sum flag
- Receive enable bit (bit 2 at addresses 03A5
- Start bit detection
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
f
address 037D
transfer buffer register to UARTi transmit register is completed
address 037D
UARTi transfer register is completed
When receiving
UARTi receive buffer register is completed
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
This error occurs when the number of stop bits set is not detected
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
T
fi/16(n+1) (Note 1) fi = f
EXT
ransmit interrupt cause select bits (bits 0 at address 03B0
/16(n+1)(Note 1) (Note 2)
16
16
) = “0”: Interrupts requested when data transfer from UARTi
) = “1”: Interrupts requested when data transmission from
1
, f
8
Specification
, f
32
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
16
16
, 037D
, 037D
M306V5ME-XXXSP
16
16
16
, 0378
, 037D
, 0378
16
16
) = “1”
) = “1”
M306V5EESP
16
16
16
16
16
= “0”) :
) = “0”
, bit4 at
=“1”) :
, bit4 at
105