M306V2 Mitsubishi, M306V2 Datasheet - Page 148

• Manufacturer Part Number: M306V2
• Description: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
• Manufacturer: Mitsubishi

148
BUSFREE:
MOV.B
BUSBUSY:
Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and
TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the SCL pin is released
and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the
MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1.” It is because it may become
the same as above.
Do not write data in the I
busy flag BB becomes “0” after generating the STOP condition in the master mode. It is because the
STOP condition waveform might not be normally generated. Reading to the above registers do not have
the problem.
START condition generating procedure using multi-master
RESTART condition generating procedure
Writing to I
Process of after STOP condition generating
Be sure to add NOP instruction
START condition generating shown the above procedure example.
When using multi-master system, disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts immediately.
When using single-master system, it is not necessary to disable interrupts above.
Use the I
And also, be sure to add NOP instruction
FCLR
BTST
JC
MOV.B
NOP
NOP
FSET
FSETI
MOV.B
NOP
NOP
MOV.B
2
2
Ci transmit buffer register to write the slave address value to the I
Ci status register
:
I
5, IICiS1
BUSBUSY
SA, IICiS0
#F0H, IICiS1
I
:
:
:
SA, IICiS0S
#F0H, IICiS1
:
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
2
Ci data shift register (IICiS0) and the I
2 between writing the slave address value and setting trigger of
2.
(Interrupt disabled)
(BB flag confirming and branch process)
(Writing of slave address value <SA>)
(Trigger of START condition generating)
(Interrupt enabled)
(Interrupt enabled)
(Writing of slave address value <SA>)
(Trigger of RESTART condition generating)
2
Ci status register (IICiS1) until the bus
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
2
Ci data shift register.
M306V2EEFP
Rev. 1.0