ST62T15C ST Microelectronics, ST62T15C Datasheet - Page 20
ST62T15C
Manufacturer Part Number
ST62T15C
Description
(ST62T15C / ST62T25C) 8-BIT OTP/EPROM MCUs WITH A/D CONVERTER
Manufacturer
ST Microelectronics
Datasheet
1.ST62T15C.pdf
(70 pages)
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ST62T15C/T25C/E25C
RESETS (Cont’d)
3.2.6 MCU Initialization Sequence
When a reset occurs the stack is reset, the PC is
loaded with the address of the Reset Vector (locat-
ed in program ROM starting at address 0FFEh). A
jump to the beginning of the user program must be
coded at this address. Following a Reset, the In-
terrupt flag is automatically set, so that the CPU is
in Non Maskable Interrupt mode; this prevents the
initialisation routine from being interrupted. The in-
itialisation routine should therefore be terminated
by a RETI instruction, in order to revert to normal
mode and enable interrupts. If no pending interrupt
is present at the end of the initialisation routine, the
MCU will continue by processing the instruction
immediately following the RETI instruction. If, how-
ever, a pending interrupt is present, it will be serv-
iced.
Figure 16. Reset Block Diagram
20/70
20
RESET
1) Resistive ESD protection. Value not guaranteed.
WATCHD OG RESET
POWER
LVD RESET
V
DD
ON RESET
R
PU
R
ESD
1)
f
OSC
AND. Wired
Figure 15. Reset and Interrupt Processing
VECTOR
RESET
RESET
INITIALIZATION
ROUTINE
RESET
CK
COUNTER
RESET
RETI
JP
JP:2 BYTES/4 CYCLES
RETI: 1 BYTE/2 CYCLES
ST6
INTERNA L
RESET
VR02107A
VA00181