TDA3566 Philips Semiconductors, TDA3566 Datasheet - Page 5

• Manufacturer Part Number: TDA3566
• Description: PAL/NTSC decoder
• Manufacturer: Philips Semiconductors

Philips Semiconductors
FUNCTIONAL DESCRIPTION
The TDA3566A is a further
development of the TDA3562A. It has
the same pinning and nearly the
same application. The differences
between the TDA3562A and the
TDA3566A are as follows:
Luminance amplifier
The luminance amplifier is voltage
driven and requires an input signal of
450 mV peak-to-peak (positive
video). The luminance delay line must
be connected between the IF
amplifier and the decoder.
The input signal is AC coupled to the
input (pin 8). After amplification, the
black level at the output of the
February 1994
The NTSC-application has largely
been simplified. In the event of
NTSC the chrominance signal is
now internally coupled to the
demodulators, automatic
chrominance control (ACC) and
phase detectors. The chrominance
output signal (pin 28) is thus
suppressed. It follows that the
external switches and filters which
are required for the TDA3562A are
not required for the TDA3566A.
There is no difference between the
amplitudes of the colour output
signals in the PAL or NTSC mode.
The clamp capacitor at pins 10, 20
and 21 in the black-level
stabilization loop can be reduced to
100 nF provided the stability of the
loop is maintained. Loop stability
depends on complete application.
The clamp capacitors receive a
pre-bias voltage to avoid coloured
background during switch-on.
The crystal oscillator circuit has
been changed to prevent parasitic
oscillations on the third overtone of
the crystal. Consequently the
optimum tuning capacitance must
be reduced to 10 pF.
The hue control has been improved
(linear).
PAL/NTSC decoder
preamplifier is clamped to a fixed DC
level by the black level clamping
circuit. During three line periods after
vertical blanking, the luminance
signal is blanked out and the black
level reference voltage is inserted by
a switching circuit.
This black level reference voltage is
controlled via pin11 (brightness). At
the same time the RGB signals are
clamped. Noise and residual signals
have no influence during clamping
thus simple internal clamping circuitry
is used.
Chrominance amplifiers
The chrominance amplifier has an
asymmetrical input. The input signal
must be AC coupled (pin 4) and have
a minimum amplitude of
40 mV peak-to-peak.
The gain control stage has a control
range in excess of 30 dB, the
maximum input signal must not
exceed 1.1 V peak-to-peak,
otherwise clipping of the input signal
will occur.
From the gain control stage the
chrominance signal is fed to the
saturation control stage. Saturation is
linearly controlled via pin 5. The
control voltage range is 2 to 4 V, the
input impedance is high and the
saturation control range is in excess
of 50 dB.
The burst signal is not affected by
saturation control. The signal is then
fed to a gated amplifier which has a
12 dB higher gain during the
chrominance signal. As a result the
signal at the output (pin 28) has a
burst-to-chrominance ratio which is
6 dB lower than that of the input
signal when the saturation control is
set at 6 dB.
The chrominance output signal is fed
to the delay line and, after matrixing,
is applied to the demodulator input
pins (pins 22 and 23). These signals
5
are fed to the burst phase detector. In
the event of NTSC the chrominance
signal is internally coupled to the
demodulators, ACC and phase
detectors.
Oscillator and identification circuit
The burst phase detector is gated
with the narrow part of the sandcastle
pulse (pin 7). In the detector the
(R Y) and (B Y) signals are added to
provide the composite burst signal
again.
This composite signal is compared
with the oscillator signal
divided-by-2 (R Y) reference signal.
The control voltage is available at
pins 24 and 25, and is also applied to
the 8.8 MHz oscillator. The 4.4 MHz
signal is obtained via the divide-by-2
circuit, which generates both the
(B Y) and (R Y) reference signals
and provides a 90 phase shift
between them.
The flip-flop is driven by pulses
obtained from the sandcastle
detector. For the identification of the
phase at PAL mode, the (R Y)
reference signal coming from the PAL
switch, is compared to the vertical
signal (R Y) of the PAL delay line.
This is carried out in the H/2 detector,
which is gated during burst.
When the phase is incorrect, the
flip-flop gets a reset from the
identification circuit. When the phase
is correct, the output voltage of the
H/2 detector is directly related to the
burst amplitude so that this voltage
can be used for the ACC.
To avoid 'blooming-up' of the picture
under weak input signal conditions
the ACC voltage is generated by peak
detection of the H/2 detector output
signal. The killer and identification
circuits receive their information from
a gated output signal of H/2 detector.
Killing is obtained via the saturation
control stage and the demodulators to
obtain good suppression.
Product specification
TDA3566A