ML4824 Fairchild, ML4824 Datasheet
ML4824
Available stocks
Related parts for ML4824
ML4824 Summary of contents
Page 1
... Power Factor Correction and PWM Controller Combo GENERAL DESCRIPTION The ML4824 is a controller for power factor corrected, switched mode power supplies. Power Factor Correction (PFC) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully complies with IEC1000-2-3 specification ...
Page 2
... RAMP 2 When in current mode, this pin functions as as the current sense input; when in voltage mode the PWM input from PFC output (feed forward ramp). 2 ML4824 16-Pin PDIP (P16) 16-Pin Wide SOIC (S16W) IEAO 1 16 VEAO ...
Page 3
... Storage Temperature Range ..................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) ..................... 260°C Thermal Resistance ( Plastic DIP ....................................................... 80°C/W Plastic SOIC ................................................... 105°C/W + 0.3V CCZ OPERATING CONDITIONS 20mA Temperature Range ML4824CX ................................................. 0°C to 70°C ML4824IX .............................................. –40°C to 85°C = 52. 470pF Operating Temperature Range (Note CONDITIONS VEAO = 3 ...
Page 4
... ML4824 ELECTRICAL CHARACTERISTICS SMBOL PARAMETER OVP COMPARATOR Threshold Voltage Hysteresis PFC I COMPARATOR LIMIT Threshold Voltage (PFC Gain Modulator Output) LIMIT TH Delay to Output DC I COMPARATOR LIMIT Threshold Voltage Input Bias Current Delay to Output V OK COMPARATOR IN Threshold Voltage Hysteresis GAIN MODULATOR Gain (Note 3) ...
Page 5
... OUT C = 1000pF L ) CCZ 25mA < I < 55mA CC Load, Temp V = 11.8V < 0.5V CCZ pin (VEAO - 1.5V MIN TYP 90 95 0.4 0.8 0.7 10 10.5 9 0-44 0-47 0-37 0-40 0.4 0.8 0.7 10 10.5 9 12.8 13.5 ±100 12.4 0 2.7 3.0 ML4824 MAX UNITS 0.8 V 2 0-50 % 0-45 % 0.8 V 2 14.2 V ±300 mV 14 ...
Page 6
... ML4824 TYPICAL PERFORMANCE CHARACTERISTICS 250 200 150 100 (V) Voltage Error Amplifier (VEA) Transconductance (g 16 VEAO V FB VEA 3.5k 15 – + 2.5V + – GAIN V RMS MODULATOR 4 3.5k I SENSE 3 RAMP Current Error Amplifier (IEA) Transconductance (g m 400 300 ...
Page 7
... PFC SECTION Gain Modulator Figure 1 shows a block diagram of the PFC section of the ML4824. The gain modulator is the heart of the PFC this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and PFC output voltage. There are three inputs to the gain modulator ...
Page 8
... SENSE will not restart until the voltage at V The V FB passive external power components and the ML4824 are within their safe operating voltages, but not so low as to interfere with the boost voltage regulation loop. Error Amplifier Compensation The PWM loading of the PFC can be modeled as a negative resistor ...
Page 9
... PFC section of the device, from which it also derives its basic timing (at the PFC frequency in the ML4824-1, and at twice the PFC frequency in the ML4824-2). The PWM is capable of current-mode or voltage mode operation. In current-mode applications, the PWM ramp (RAMP 2) is ...
Page 10
... Typically, a 1.0 F soft start capacitor will allow time for V prior to activation of the PWM section at line voltages between 90Vrms and 265Vrms. Generating V The ML4824 is a current-fed part. It has an internal shunt is less than its voltage regulator, which is designed to regulate the voltage FB internal to the part at 13.5V. This allows a low power dissipation while at the same time delivering 10V of gate drive at the PWM OUT and PFC OUT outputs ...
Page 11
... Figure 6 is the application circuit for a complete 100W power factor corrected power supply, designed using the methods and general topology detailed in Application Note 33. SW2 SW1 C1 U3 DFF + R Q – CLK Figure 4. Typical Trailing Edge Control Scheme. ML4824 RAMP VEAO TIME VSW1 TIME 11 ...
Page 12
... ML4824 VIN DC + – REF OSC U4 12 SW2 SW1 VEAO DFF CMP + RAMP R Q – CLK Q CLK Figure 5. Typical Leading Edge Control Scheme. RAMP VEAO TIME VSW1 TIME REV. 1.01 12/7/2000 ...
Page 13
... C14 2.37k 100nF 1µF C15 C16 82nF 10nF 1µF D10 1A, 20V L1: Premier Magnetics #TSD-734 L2: 33µH, 10A DC T1: Premier Magnetics #TSD-736 T2: Premier Magnetics #TSD-735 Premier Magnetics: (714) 362-4211 ML4824 12VDC C24 1µF RTN R24 1.2k R18 R22 220 8.66k R25 2.26k C9 8.2nF C8 ...
Page 14
... ML4824 PHYSICAL DIMENSIONS 16 PIN 0.02 MIN (0.50 MIN) (4 PLACES) 0.170 MAX (4.32 MAX) 0.125 MIN (3.18 MIN) 14 inches (millimeters) Package: P16 16-Pin PDIP 0.740 - 0.760 (18.79 - 19.31) 0.240 - 0.260 (6.09 - 6.61) 0.055 - 0.065 0.100 BSC (1.40 - 1.65) (2.54 BSC) 0.015 MIN (0.38 MIN) SEATING PLANE 0.016 - 0.022 (0.40 - 0.56) 0.295 - 0.325 (7.49 - 8.26) 0.008 - 0.012 0º - 15º ...
Page 15
... PHYSICAL DIMENSIONS 0.400 - 0.414 (10.16 - 10.52) 16 PIN 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.012 - 0.020 0.090 - 0.094 (0.30 - 0.51) (2.28 - 2.39) REV. 1.01 12/7/2000 inches (millimeters) Package: S16W 16-Pin Wide SOIC 0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0º - 8º 0.005 - 0.013 SEATING PLANE (0.13 - 0.33) ML4824 0.022 - 0.042 0.009 - 0.013 (0.56 - 1.07) (0.22 - 0.33) 15 ...
Page 16
... PART NUMBER ML4824CP-1 ML4824CP-2 ML4824CS-1 ML4824CS-2 ML4824IP-1 ML4824IP-2 ML4824IS-1 ML4824IS-2 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; ...