HIP6004E Intersil Corporation, HIP6004E Datasheet - Page 9

• Manufacturer Part Number: HIP6004E
• Description: Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor
• Manufacturer: Intersil Corporation

where: I
response time to the application of load, and t
response time to the removal of load. With a +5V input
source, the worst-case response time can be either at the
application or removal of load and dependent upon the
DACOUT setting. Be sure to check both of these equations
at the minimum and maximum output levels for the worst
case response time. With a +12V input, and output voltage
level equal to DACOUT, t
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high-frequency decoupling and bulk capacitors
to supply the current needed each time Q
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
For a through-hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These capacitors
must be capable of handling the surge current at power-up.
Some capacitor series available from reputable manufacturers
are surge current tested.
MOSFET Selection/Considerations
The HIP6004E requires 2 N-Channel power MOSFETs. These
should be selected based upon r
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed between
the two MOSFETs according to duty factor (see the equations
below). Only the upper MOSFET has switching losses, since
the Schottky rectifier clamps the switching node before the
synchronous rectifier turns on. These equations assume linear
voltage current transitions and do not adequately model power
loss due the reverse recovery of the lower MOSFET’s body
diode. The gate-charge losses are dissipated by the HIP6004E
and don't heat the MOSFETs. However, large gate charge
increases the switching interval, t
MOSFET switching losses. Ensure that both MOSFETs are
TRAN
is the transient load current step, t
FALL
1
and the source of Q
9
is the longest response time.
DS(ON)
SW
which increases the upper
, gate supply
1
turns on. Place the
FALL
2
RISE
.
is the
is the
HIP6004E
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
Standard-gate MOSFETs are normally recommended for
use with the HIP6004E. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFET’s absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by a
bootstrap circuit from V
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V
less the boot diode drop (V
turns on. Logic-level MOSFETs can only be used if the
MOSFET’s absolute gate-to-source voltage rating exceeds
the maximum voltage applied to VCC.
Figure 10 shows the upper gate drive supplied by a direct
connection to V
converter systems where the main input voltage is +5V
less. The peak upper gate-to-source voltage is approximately
V
for the bias, the gate-to-source voltage of Q
level MOSFET is a good choice for Q
MOSFET can be used for Q
voltage rating exceeds the maximum voltage applied to V
P
Where: D is the duty cycle = V
P
CC
UPPER
LOWER
+
-
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
HIP6004E
less the input supply. For +5V main power and +12V
+12V
VCC
t
F
SW
= Io
S
= Io
is the switching frequency.
is the switch ON time, and
2
2
x r
x r
CC
DS(ON)
DS(ON)
+ V
GND
D
. This option should only be used in
BOOT
BOOT
UGATE
PHASE
LGATE
PGND
D
-
CC
x D +
x (1 - D)
. The boot capacitor, C
D
OUT
C
2
) when the lower MOSFET, Q
1
2
BOOT
if its absolute gate-to-source
Io x V
/ V
IN
Q1
Q2
+5V OR +12V
,
IN
1
and a logic-level
x t
SW
1
D2
is 7V. A logic-
x F
NOTE:
V
NOTE:
V
G-S
G-S
S
BOOT
V
V
CC
CC
DC
CC
-V
CC
DC
2
or
D
.