HIP6004E Intersil Corporation, HIP6004E Datasheet - Page 7

• Manufacturer Part Number: HIP6004E
• Description: Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor
• Manufacturer: Intersil Corporation

Figure 5 shows the critical power components of the converter.
To minimize the voltage overshoot the interconnecting wires
indicated by heavy lines should be part of ground or power
plane in a printed circuit board. The components shown in
Figure 5 should be located as close together as possible.
Please note that the capacitors C
numerous physical capacitors. Locate the HIP6004E within 3
inches of the MOSFETs, Q
MOSFETs’ gate and source connections from the HIP6004E
must be sized to handle up to 1A peak current.
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS pin and locate the capacitor, C
close to the SS pin because the internal current source is
only 10 A. Provide local V
GND pins. Locate the capacitor, C
practical to the BOOT and PHASE pins.
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
error amplifier (Error Amp) output (V
the oscillator (OSC) triangular wave to provide a pulse-
width modulated (PWM) wave with an amplitude of V
the PHASE node.
C
OUT
FIGURE 5. PRINTED CIRCUIT BOARD POWER AND
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
SS
SS
HIP6004E
) is regulated to the Reference voltage level. The
HIP6004E
UGATE
PHASE
LGATE
PGND
GND
GROUND PLANES OR ISLANDS
LAYOUT GUIDELINES
BOOT
PHASE
VCC
C
BOOT
1
CC
+12V
Q
Q
V
and Q
RETURN
IN
2
1
decoupling between VCC and
7
C
D
VCC
IN
D
1
2
BOOT
2
and C
. The circuit traces for the
E/A
C
O
) is compared with
as close as
Q
IN
+V
Q
1
each represent
2
L
IN
O
L
C
O
O
C
O
V
OUT
IN
SS
V
OUT
at
HIP6004E
The PWM wave is smoothed by the output filter (L
The modulator transfer function is the small-signal transfer
function of V
Gain and the output filter (L
break frequency at F
the modulator is simply the input voltage (V
peak-to-peak oscillator voltage V
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the HIP6004E) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180 degrees The equations below relate the compensation
network’s poles, zeros and gain to the components (R
R
locating the poles and zeros of the compensation network:
F LC
1. Pick Gain (R
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
3
V
FIGURE 7. VOLTAGE-MODE BUCK CONVERTER
OSC
, C
=
FB
1
------------------------------------------ -
2 x L O x C O
, C
. The goal of the compensation network is to provide
OSC
2
ST
, and C
ND
ST
ND
0dB
OUT
COMPARATOR
1
COMPENSATION DESIGN
Zero Below Filter’s Double Pole (~75% F
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
Pole at the ESR Zero.
V
Zero at Filter’s Double Pole.
Pole at Half the Switching Frequency.
HIP6004E
) and adequate phase margin. Phase margin
E/A
2
PWM
/V
/R
3
Z
+
E/A
-
) in Figure 7. Use these guidelines for
1
-
+
FB
COMP
LC
) for desired converter bandwidth.
C
. This function is dominated by a DC
1
REFERENCE
and a zero at F
C
DACOUT
-
+
2
O
DRIVER
DRIVER
R
F ESR
and C
Z
2
IN
OSC
FB
=
O
Z
------------------------------------------- -
2 x ESR x C
FB
), with a double pole
ESR
.
PHASE
V
(PARASITIC)
C
IN
3
IN
L
Z
R
. The DC Gain of
1
IN
O
1
) divided by the
R
ESR
3
C
O
V
O
OUT
O
and C
0dB
V
LC
1
OUT
, R
and
).
O
IN
2
).
,