XC68HC05P18A Motorola, XC68HC05P18A Datasheet - Page 70

• Manufacturer Part Number: XC68HC05P18A
• Description: HCMOS Microcontroller Unit
• Manufacturer: Motorola

16-Bit Timer
8.5 Input Capture
Technical Data
70
NOTE:
Address:
Address:
Two 8-bit read-only registers (ICRH and ICRL) make up the 16-bit input
capture. They are used to latch the value of the free-running counter
after a defined transition is sensed by the input capture edge detector.
The input capture edge detector contains a Schmitt trigger to improve
noise immunity.
The edge that triggers the counter transfer is defined by the input edge
bit (IEDG) in TCR. Reset does not affect the contents of the input
capture registers. See
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the PH2 clock preceding
the external transition (see
synchronization. Resolution is affected by the prescaler, allowing the
free-running counter to increment once every four PH2 clock cycles.
The contents of the free-running counter are transferred to the input
capture registers on each proper signal transition regardless of the state
of the input capture flag bit (ICF) in register TSR. The input capture
registers always contain the free-running counter value which
corresponds to the most recent input capture.
Reset:
Reset:
Read:
Read:
Write:
Write:
ICRH7
$0014
$0015
ICRL7
Bit 7
Bit 7
Figure 8-8. Input Capture Registers (ICRH/ICRL)
ICRH6
ICRL6
6
6
16-Bit Timer
Figure
ICRH5
ICRL5
5
5
Figure
8-8.
Unaffected by reset
Unaffected by reset
ICRH4
ICRL4
8-9). This delay is required for internal
4
4
ICRH3
ICRL3
3
3
ICRH2
ICRL2
2
2
ICRH1
ICRL1
MC68HC05P18A
1
1
MOTOROLA
ICRH0
ICRL0
Bit 0
Bit 0