XC68HC05P18A Motorola, XC68HC05P18A Datasheet - Page 65
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XC68HC05P18A
Manufacturer Part Number
XC68HC05P18A
Description
HCMOS Microcontroller Unit
Manufacturer
Motorola
Datasheet
1.XC68HC05P18A.pdf
(130 pages)
- Current page: 65 of 130
- Download datasheet (2Mb)
8.3 Timer
MC68HC05P18A
MOTOROLA
NOTE:
Because the timer has a 16-bit architecture, each function is represented
by two registers. Each register pair contains the high and low byte of that
function. Generally, accessing the low byte of a specific timer function
allows full control of that function; however, an access of the high byte
inhibits that specific timer function until the low byte is also accessed.
The I bit in the condition code register (CCR) should be set while
manipulating both the high and low byte registers of a specific timer
function. This prevents interrupts from occurring between the time that
the high and low bytes are accessed.
The key element of the programmable timer is a 16-bit free-running
counter, or timer registers, preceded by a prescaler, which divides the
PH2 clock by four. The prescaler gives the timer a resolution of 2.0 ms
when a 4-MHz crystal is used. The counter is incremented to increasing
values during the low portion of the PH2 clock cycle.
The double byte free-running counter can be read from either of two
locations:
Both locations will contain identical values. A read sequence containing
only a read of the least-significant bit (LSB) of the counter (TMRL/ACRL)
returns the count value at the time of the read. If a read of the counter
accesses the most-significant bit (MSB) first (TMRH/ACRH), it causes
the LSB (TMRL/ACRL) to be transferred to a buffer. This buffer value
remains fixed after the first MSB byte read even if the MSB is read
several times. The buffer is accessed when reading the counter LSB
(TMRL/ACRL), and thus completes a read sequence of the total counter
value. When reading either the timer or alternate counter registers, if the
MSB is read, the LSB must also be read to complete the read sequence.
See
•
•
Figure 8-2
The timer registers, TMRH and TMRL
The alternate counter registers, ACRH and ACRL
and
16-Bit Timer
Figure
8-3.
Technical Data
16-Bit Timer
Timer
65
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