DSM2190F4 STMicroelectronics, DSM2190F4 Datasheet - Page 39

• Manufacturer Part Number: DSM2190F4
• Description: DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-2191 DSPs (3.3V Supply)
• Manufacturer: STMicroelectronics

Figure 24. Reset (RESET) Timing
Power On Reset, Warm Reset, Power-down
Power On Reset. Upon Power-up, the device re-
quires a Reset (
after V
vice loads internal configurations, clears some of
the registers and sets the Flash memory into Op-
erating mode. After the rising edge of Reset (
SET
additional period, t
cess is allowed.
Table 19. Status During Power-On Reset, Warm Reset and Power-down Mode
Warm Reset. Once the device is up and running,
the device can be reset with a pulse of a much
shorter duration, t
needed before the device is operational after
warm reset. Figure 24 shows the timing of the
Power-up and warm reset.
I/O Pin, Register and PLD Status at Reset. Ta-
ble 19 shows the I/O pin, register and PLD status
during Power On Reset, warm reset and Power-
MCU I/O
PLD Output
PMMR0 and PMMR2
OMC Flip-flop status
All other registers
), the device remains in the Reset mode for an
Port Configuration
V
RESET
CC
CC
Register
is steady. During this time period, the de-
RESET
NLNH
OPR
, before the first memory ac-
) pulse of duration t
Power-On Reset
. The same t
V
t NLNH-PO
CC
(min)
Input mode
Valid after internal PSD
configuration bits are
loaded
Cleared to 0
Cleared to 0 by internal
Power-On Reset
Cleared to 0
Power-On Reset
Power-On Reset
OPR
period is
NLNH-PO
t OPR
RE-
Input mode
Valid
Unchanged
Depends on .re and .pr
equations
Cleared to 0
The Flash memory is reset to the Read Array
mode upon Power-up. Sector Select FS0-FS7
must all be Low, Write Strobe (
during Power On Reset for maximum security of
the data contents and to remove the possibility of
a byte being written on the first edge of Write
Strobe (
cle initiation is prevented automatically when V
is below V
down mode. PLD outputs are always valid during
warm reset, and they are valid in Power On Reset
once the internal device Configuration bits are
loaded. This loading of the device is completed
typically long before the V
ing level. Once the PLD is active, the state of the
outputs are determined by the PSDsoft Express
equations.
Warm Reset
Warm Reset
WR
LKO
, CNTL0). Any Flash memory Write cy-
.
Warm Reset
t NLNH-A
t NLNH
Unchanged
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Unchanged
Depends on .re and .pr
equations
Unchanged
CC
Power-down Mode
Power-down Mode
ramps up to operat-
WR
, CNTL0) High,
DSM2190F4
t OPR
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CC