HYB18T512400AC Infineon Technologies AG, HYB18T512400AC Datasheet - Page 2

• Manufacturer Part Number: HYB18T512400AC
• Description: DDR2 Registered Memory Modules
• Manufacturer: Infineon Technologies AG

Low Profile 240-pin Registered DDR2 SDRAM Modules Datasheet
512 MByte, 1 GByte & 2 GByte Modules
PC2-3200R, PC2-4300R
• 240-pin Registered 8-Byte ECC Dual-In-Line
• One rank 64Mb x 72, 128Mb x 72 and
• JEDEC standard Double Data Rate 2
• 512MB and 1 GB modulesModules built with
• Two versions of 2 GB modules
1.0 Description
The INFINEON HYS72Taaabcd[G/H]R module family are low profile Registered DIMM modules
with 30,00 mm height based on DDR2 technology. DIMMs are available in 64M x 72 (512MByte),
128M x 72 (1GByte) and 256M x 72 (2GByte) organisation and density, intended for mounting into
240 pin connector sockets.
The memory array is designed with 512Mb Double Data Rate (DDR2) Synchronous DRAMs for
ECC applications. All control and address signals are re-driven on the DIMM using register devices
and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one
cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board, which provide
a proper voltage supply impedance over the whole frequency range of operations as number and
values are accordant to the JEDEC specification. The DIMMs feature serial presence detect based
on a serial E
configuration data and the second 128 bytes are available to the customer.
Performance:
Speed Grade Indicator
Component Speed Grade on Module
Module Speed Grade
Max. Clock Frequency @ CL = 3
Max. Clock Frequency@ CL = 4 & 5
DDR2 SDRAM Module for PC, Workstation
and Server main memory applications
two ranks 128Mb
organizations
Synchronous DRAMs (DDR2 SDRAMs) with
+ 1.8 V ( 0.1 V) power supply
512Mb DDR2 SDRAMs in 60-ball FBGA
chipsize packages
built with 63-ball FBGA dual die chipsiz
(
2 x 512Mb components) or 60-ball FBGA packages
2
PROM device using the 2-pin I
72 and 256Mb x 72
e packages
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Preliminary Data Sheet Rev. 0.85 (Apr. 2004)
2
C protocol. The first 128 bytes are programmed with
2
• Programmable CAS Latencies (3, 4 & 5),
• Auto Refresh and Self Refresh
• All inputs and outputs SSTL_1.8 compatible
• Re-drive for all input signals using register
• OCD (Off-Chip Driver Impedance
• Serial Presence Detect with E
• Low Profile Modules form factor:
• Based on JEDEC standard reference card
Burst Length (4 & 8) and Burst Type.
and PLL devices.
Adjustment) and ODT (On-Die Termination)
133.35 mm x 30,00 mm (MO-237)
designs
PC2–3200R
DDR2–400
200
200
–5
PC2–4300R
DDR2–533
–3.7
200
266
Rev. 0.85, 2004-04
2
PROM
Unit
MHz
MHz