M24M01 STMicroelectronics, M24M01 Datasheet - Page 6

• Manufacturer Part Number: M24M01
• Description: 1 Mbit Serial IC Bus EEPROM
• Manufacturer: STMicroelectronics

M24M01
Figure 6. Write Mode Sequences with WC=1 (data write inhibited)
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the RW bit reset to 0.
The device acknowledges this, as shown in Figure
7, and waits for two address bytes. The device re-
sponds to each address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if Write
Control (WC) is driven High. Any Write instruction
with Write Control (WC) driven High (during a pe-
riod of time from the Start condition until the end of
the two address bytes) will not modify the memory
contents, and the accompanying data bytes are
not acknowledged, as shown in Figure 6.
Each data byte in the memory has a 17-bit ad-
dress. The most significant bit, A16, is sent with
the Device Select Code, and the remaining bits,
A15-A0, in the two address bytes. The Most Sig-
nificant Byte is sent first, followed by the Least Sig-
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WC
BYTE WRITE
WC
PAGE WRITE
WC (cont'd)
PAGE WRITE
(cont'd)
NO ACK
DEV SEL
DEV SEL
DATA IN N
R/W
R/W
ACK
ACK
NO ACK
BYTE ADDR
BYTE ADDR
ACK
ACK
BYTE ADDR
BYTE ADDR
nificant Byte. Bits A16 to A0 form the address of
the byte in memory.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
During the internal Write cycle, Serial Data (SDA)
is disabled internally, and the device does not re-
spond to any requests.
Byte Write
After the Device Select code and the address
bytes, the bus master sends one data byte. If the
addressed location is Write-protected, by Write
Control (WC) being driven High, the device replies
with NoAck, and the location is not modified. If, in-
stead, the addressed location is not Write-protect-
ed, the device replies with Ack. The bus master
ACK
ACK
DATA IN 1
DATA IN
NO ACK
NO ACK
DATA IN 2
AI01120C
th
bit” time