M95256-RBN6T ST Microelectronics, M95256-RBN6T Datasheet - Page 9
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M95256-RBN6T
Manufacturer Part Number
M95256-RBN6T
Description
256/128 Kbit Serial SPI Bus EEPROM With High Speed Clock
Manufacturer
ST Microelectronics
Datasheet
1.M95256-RBN6T.pdf
(21 pages)
Figure 11. Byte Write Operation Sequence
Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
next address, can be read by successive clock
pulses. When the highest address is reached, the
address counter rolls over to “0000h”, allowing the
read cycle to be continued indefinitely. The read
operation is terminated by deselecting the chip.
The chip can be deselected at any time during
data output. If a read instruction is received during
Figure 12. Page Write Operation Sequence
Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
S
C
D
Q
S
C
D
S
C
D
7
32
0
0
6
33
1
1
DATA BYTE 2
HIGH IMPEDANCE
5
34
INSTRUCTION
INSTRUCTION
2
2
4
35 36 37 38 39 40 41 42
3
3
3
4
4
2
5
5
1
6
6
0
7
7
7
15
15
8
8
6
14 13
14 13
9 10
9 10
16 BIT ADDRESS
16 BIT ADDRESS
DATA BYTE 3
5
4
43
a write cycle, it is rejected, and the memory device
deselects itself.
Byte Write Operation
Before any write can take place, the WEL bit must
be set, using the WREN instruction. The write
state is entered by selecting the chip, issuing three
3
44 45 46 47
3
3
20 21 22 23 24 25 26 27
20 21 22 23 24 25 26 27
2
2
2
1
1
1
0
0
0
7
7
6
6
6
DATA BYTE N
5
DATA BYTE 1
5
5
DATA BYTE
4
4
4
3
3
3
28 29 30
28 29 30
2
2
2
1
M95256, M95128
1
1
0
0
0
31
31
AI01796
AI01795
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