M95256-RBN6T ST Microelectronics, M95256-RBN6T Datasheet - Page 10

• Manufacturer Part Number: M95256-RBN6T
• Description: 256/128 Kbit Serial SPI Bus EEPROM With High Speed Clock
• Manufacturer: ST Microelectronics

M95256, M95128
bytes of instruction and address, and one byte of
data. Chip Select (S) must remain low throughout
the operation, as shown in Figure 11. The product
must be deselected just after the eighth bit of the
data byte has been latched in, otherwise the write
process is cancelled. As soon as the memory
device is deselected, the self-timed internal write
cycle is initiated. While the write is in progress, the
status register may be read to check the status of
the SRWD, BP1, BP0, WEL and WIP bits. In
particular, WIP contains a ‘1’ during the self-timed
write cycle, and a ‘0’ when the cycle is complete,
(at which point the write enable latch is also reset).
Page Write Operation
A maximum of 64 bytes of data can be written
during one Write time, t
to the same page (see Figure 6). The Page Write
operation is the same as the Byte Write operation,
except that instead of deselecting the device after
the first byte of data, up to 63 additional bytes can
be shifted in (and then the device is deselected
after the last byte).
Any address of the memory can be chosen as the
first address to be written. If the address counter
reaches the end of the page (an address of the
form xxxx xx11 1111) and the clock continues, the
counter rolls over to the first address of the same
page (xxxx xx00 0000) and over-writes any
previously written data.
As before, the Write cycle only starts if the S
transition occurs just after the eighth bit of the last
data byte has been received, as shown in Figure
12.
Table 8. Initial Status Register Format
Table 9. AC Measurement Conditions
Note: 1. Output Hi-Z is defined as the point where data is no
Table 10. Input Parameters
Note: 1. Sampled only, not 100% tested.
10/21
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing
Reference Voltages
Output Load
b7
0
Symbol
C
C
longer driven.
OUT
IN
0
0
Output Capacitance (Q)
Input Capacitance (other pins)
0
W
, provided that they are all
Parameter
0
1
(T
A
0.2V
0.3V
0
= 25 °C, f = 5 MHz)
C
L
CC
CC
= 100 pF
50 ns
0
to 0.8V
to 0.7V
b0
0
CC
CC
Test Condition
DATA PROTECTION AND PROTOCOL SAFETY
To protect the data in the memory from inadvertent
corruption, the memory device only responds to
correctly
security measures can be summarized as follows:
– The WEL bit is reset at power-up.
– S must rise after the eighth clock count (or
– Accesses to the memory array are ignored
– After execution of a WREN, WRDI, or RDSR
– Invalid S and HOLD transitions are ignored.
POWER ON STATE
After power-on, the memory device is in the
following state:
– low power stand-by state
– deselected (after power-on, a high-to-low
– not in the hold condition
– the WEL bit is reset
– the SRWD, BP1 and BP0 bits of the status
INITIAL DELIVERY STATE
The device is delivered with the memory array in a
fully erased state (all data set at all “1’s” or FFh).
The status register bits are initialized to 00h, as
shown in Table 8.
Figure 13. AC Testing Input Output Waveforms
0.8V CC
0.2V CC
multiple thereof) in order to start a non-volatile
write cycle (in the memory array or in the status
register).
during the non-volatile programming cycle, and
the programming cycle continues unaffected.
instruction, the chip enters a wait state, and
waits to be deselected.
transition is required on the S input before any
operations can be started).
register are un-changed from the previous
power-down (they are non-volatile bits).
formulated
Min.
commands.
Max.
8
6
The
Unit
0.7V CC
0.3V CC
AI00825
pF
pF
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