M95640 ST Microelectronics, M95640 Datasheet - Page 7

• Manufacturer Part Number: M95640
• Description: 64/32/16/8 Kbit Serial SPI Bus EEPROM With High Speed Clock
• Manufacturer: ST Microelectronics

CONNECTING TO THE SPI BUS
These devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Serial Clock (C) after Chip
Select (S) goes Low.
All output data bytes are shifted out of the device,
most significant bit first. The Serial Data Output
Figure 5. Bus Master and Memory Devices on the SPI Bus
Note: 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
SPI Modes
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
SPI Interface with
(CPOL, CPHA) =
CS3
(0, 0) or (1, 1)
(ST6, ST7, ST9,
ST10, Others)
Bus Master
CS2
CS1
SDO
SDI
SCK
S
SPI Memory
C Q D
Device
W
HOLD
(Q) is latched on the first falling edge of the Serial
Clock (C) after the instruction (such as the Read
from Memory Array and Read Status Register in-
structions) have been clocked into the device.
Figure 5 shows three devices, connected to an
MCU, on a SPI bus. Only one device is selected at
a time, so only one device drives the Serial Data
Output (Q) line at a time, all the others being high
impedance.
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 6, is the clock polarity when the bus mas-
ter is in Stand-by mode and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
S
SPI Memory
C Q D
Device
W
HOLD
S
SPI Memory
M95640, M95320
C Q D
Device
W
AI03746D
HOLD
7/39