93LC56-ISL Microchip Technology, 93LC56-ISL Datasheet - Page 6

• Manufacturer Part Number: 93LC56-ISL
• Description: 1K/2K/4K 2.0V Microwire Serial EEPROM
• Manufacturer: Microchip Technology

93LC46/56/66
3.4
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
The ERASE cycle takes 4 ms per word (Typical).
FIGURE 3-2:
FIGURE 3-3:
DS11168L-page 6
CLK
DO
CLK
CS
DI
DO
CS
DI
Guarantee at Vcc = +4.5V to +6.0V.
CSL
ERASE
). DO at logical “0” indicates that program-
TRI-STATE
TRI-STATE
ERASE TIMING
ERAL TIMING
1
1
0
1
0
1
An
1
An-1
0
An-2
• • •
3.5
The Erase All (ERAL) instruction will erase the entire
memory array to the logical “1” state. The ERAL cycle
is identical to the ERASE cycle except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS. Clocking of
the CLK pin is not necessary after the device has
entered the self clocking mode. The ERAL instruction is
guaranteed at Vcc = +4.5V to +6.0V.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
The ERAL cycle takes 15 ms maximum (8 ms typical).
A0
CSL
Erase All (ERAL)
) and before the entire write cycle is complete.
T
CSL
T
CSL
T
CHECK STATUS
WC
BUSY
T
T
EC
SV
CHECK STATUS
BUSY
1997 Microchip Technology Inc.
T
SV
READY
READY
T
CZ
STANDBY
TRI-STATE
STANDBY
TRI-STATE
T
CZ