93LC56-ISL Microchip Technology, 93LC56-ISL Datasheet
93LC56-ISL
Related parts for 93LC56-ISL
93LC56-ISL Summary of contents
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... A standby current (typical) at 3.0V • ORG pin selectable memory configuration - 128 16-bit organization (93LC46) - 256 128 x 16-bit organization(93LC56) - 512 256 x 16-bit organization(93LC66) • Self-timed ERASE and WRITE cycles (including auto-erase) • Automatic ERAL before WRAL • ...
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... T WL Endurance 93LC46 — 93LC56/66 — Note 1: This parameter is tested at Tamb = 25˚C and F 2: Typical program cycle time per word. 3: This parameter is periodically sampled and not 100% tested. 4: This application is not tested but guaranteed by characterization. For endurance estimates in a specific applica- tion, please consult the Total Endurance Model which can be obtained on our BBS or website ...
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... Table 2-6). CLK and DI then become don't care inputs waiting for a new START condition to be detected. Note: CS must go low between consecutive instructions. 1997 Microchip Technology Inc. 2.3 Data In (DI) Data In (DI) is used to clock in a START bit, opcode, address, and data synchronously with the CLK input. 2.4 ...
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... READ WRITE WRAL TABLE 2-4 INSTRUCTION SET FOR 93LC56: ORG = ORGANIZATION) Instruction SB Opcode ERASE 1 11 ERAL 1 00 EWDS 1 00 EWEN 1 00 ...
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... (PROGRAM 1997 Microchip Technology Inc. 3.2 Data In (DI) and Data Out (DO possible to connect the Data In (DI) and Data Out (DO) pins together. However, with this configuration logic-high level possible for a “bus conflict” to occur during the “dummy zero” that precedes the READ operation. Under such a condition the voltage level seen undefi ...
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... CSL The ERAL cycle takes 15 ms maximum (8 ms typical). T CSL An-1 An-2 • • • CSL 0 CHECK STATUS STANDBY TRI-STATE READY BUSY WC STANDBY CHECK STATUS TRI-STATE READY BUSY T EC 1997 Microchip Technology Inc. ...
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... EWDS TIMING CS CLK FIGURE 3-5: EWEN TIMING FIGURE 3-6: READ TIMING 1997 Microchip Technology Inc. 93LC46/56/66 3.7 READ The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 8-bit (x8 organization) or 16-bit (x16 organization) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specifi ...
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... CSL The WRAL cycle takes 30 ms maximum (16 ms typical). T CSL • • • • • • BUSY • • • • • • +4. STANDBY TRI_STATE READY CSL STANDBY BUSY READY TRI-STATE T WL 1997 Microchip Technology Inc. ...
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... NOTES: 1997 Microchip Technology Inc. 93LC46/56/66 DS11168L-page 9 ...
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... NOTES: DS11168L-page 10 1997 Microchip Technology Inc. ...
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... Microwire Serial EEPROM 93LC56T 2K Microwire Serial EERPOM, Tape and Reel 93LC56X 2K Microwire Serial EEPROM in alternate pinouts (SN package only) 93LC56XT 2K Microwire Serial EEPROM in alternate pinouts, Tape and Reel (SN package only) 93LC66 4K Microwire Serial EEPROM 93LC66T 4K Microwire Serial EERPOM, Tape and Reel ...
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... Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip ...