24LC32A-MT MicrochipTechnology, 24LC32A-MT Datasheet - Page 5

• Manufacturer Part Number: 24LC32A-MT
• Description: 32KI2CSerialEEPROMinISOMicromodule
• Manufacturer: MicrochipTechnology

4.0
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
• During data transfer, the data line must remain
4.1
Both data and clock lines remain HIGH.
4.2
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
4.3
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
4.4
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
FIGURE 4-1:
FIGURE 4-2:
Accordingly, the following bus conditions have been
defined (See Figure 4-1).
SCL
SDA
1997 Microchip Technology Inc.
is not busy.
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
SCL
SDA
Transmitter must release the SDA line at this point allowing the Receiver
to pull the SDA line low to acknowledge the previous eight bits of data.
(A)
BUS CHARACTERISTICS
Bus not Busy (A)
Start Data Transfer (B)
Stop Data Transfer (C)
Data Valid (D)
CONDITION
START
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
ACKNOWLEDGE TIMING
1
2
Data from transmitter
3
4
ACKNOWLEDGE
DATA OR
VALID
5
(D)
6
TO CHANGE
ALLOWED
7
DATA
Acknowledge
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
4.5
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse.
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this
case, the slave (24LC32A) will leave the data line HIGH
to enable the master to generate the STOP condition.
(See Figure 4-2)
8
Note:
24LC32A MODULE
Bit
9
Acknowledge
The 24LC32A does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
(D)
1
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Data from transmitter
2
3
DS21225A-page 5
CONDITION
STOP
Of course,
(C)
(A)