24LC32A-MT MicrochipTechnology, 24LC32A-MT Datasheet - Page 3

• Manufacturer Part Number: 24LC32A-MT
• Description: 32KI2CSerialEEPROMinISOMicromodule
• Manufacturer: MicrochipTechnology

TABLE 1-3:
FIGURE 1-1:
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
START condition hold
time
START condition setup
time
Data input hold time
Data input setup time
STOP condition setup
time
Output valid from clock
Bus free time
Output fall time from V
min to V
Input filter spike sup-
pression (SDA and SCL
pins)
Write cycle time
Note 1: Not 100% tested. C
SCL
1997 Microchip Technology Inc.
SDA
OUT
SDA
IN
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
3: The combined T
Parameter
T
IL
SU
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
and spike suppression. This eliminates the need for a Ti specification for standard operation.
max
:
STA
AC CHARACTERISTICS
BUS TIMING DATA
T
SP
IH
T
AA
SP
Symbol
T
T
T
T
T
T
T
HD
SU
HD
SU
SU
T
F
T
T
T
T
and V
HIGH
LOW
T
T
T
CLK
BUF
WR
B
AA
OF
SP
:
:
:
:
:
F
R
F
DAT
STO
STA
STA
DAT
= total capacitance of one bus line in pF.
T
HYS
LOW
Vcc = 2.5 - 6.0V
T
4000
4700
4000
4700
4000
4700
Min
250
STD. MODE
specifications are due to Schmitt trigger inputs which provide improved noise
HD
—
—
—
—
—
—
—
0
:
STA
T
HIGH
1000
3500
Max
100
300
250
T
—
—
—
—
—
—
—
—
50
5
HD
:
DAT
Vcc = 4.5 - 6.0V
+0.1C
1300
1300
Min
600
600
600
100
600
FAST MODE
20
—
—
—
—
—
—
0
T
AA
B
24LC32A MODULE
Max
400
300
300
900
250
T
50
—
—
—
—
—
—
—
—
5
SU
:
DAT
Units
kHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
SU
:
STO
Note 1
Note 1
After this period the first clock pulse
is generated
Only relevant for repeated START
condition
Note 2
Time the bus must be free before a
new transmission can start
Note 1, C
Note 3
Byte or Page mode
T
R
B
Remarks
100 pF
T
BUF
DS21225A-page 3