LP2997MX National Semiconductor, LP2997MX Datasheet - Page 7

• Manufacturer Part Number: LP2997MX
• Description: DDR-II Termination Regulator
• Manufacturer: National Semiconductor

Block Diagram
Description
The LP2997 is a linear bus termination regulator designed to
meet the JEDEC requirements of SSTL-18. The output, V
is capable of sinking and sourcing current while regulating
the output voltage equal to VDDQ / 2. The output stage has
been designed to maintain excellent load regulation while
preventing shoot through. The LP2997 also incorporates two
distinct power rails that separates the analog circuitry from
the power output stage. This allows a split rail approach to
be utilized to decrease internal power dissipation. It also
permits the LP2997 to provide a termination solution for the
next generation of DDR-SDRAM memory (DDRII).
Pin Descriptions
AVIN AND PVIN
AVIN and PVIN are the input supply pins for the LP2997.
AVIN is used to supply all the internal control circuitry. PVIN,
however, is used exclusively to provide the rail voltage for
the output stage used to create V
capability to work off separate supplies, under the condition
that AVIN is always greater than or equal to PVIN. For
SSTL-18 applications, it is recommended to connect PVIN to
the 1.8V rail used for the memory core and AVIN to a rail
within its operating range of 2.2V to 5.5V (typically a 2.5V
supply). PVIN should always be used with either a 1.8V or
2.5V rail. This prevents the thermal limit from tripping be-
cause of excessive internal power dissipation. If the junction
temperature exceeds the thermal shutdown than the part will
enter a shutdown state identical to the manual shutdown
where V
such as 1.5V can be used but it will reduce the maximum
output current, therefore it is not recommended for most
termination schemes.
VDDQ
VDDQ is the input used to create the internal reference
voltage for regulating V
ated from a resistor divider of two internal 50kΩ resistors.
This guarantees that V
optimal implementation of VDDQ is as a remote sense. This
can be achieved by connecting VDDQ directly to the 1.8V
rail at the DIMM instead of PVIN. This ensures that the
reference voltage tracks the DDR memory rails precisely
without a large voltage drop from the power lines. For
SSTL-18 applications VDDQ will be a 1.8V signal, which will
TT
is tri-stated and V
TT
TT
will track VDDQ / 2 precisely. The
. The reference voltage is gener-
REF
remains active. A lower rail
TT
. These pins have the
TT
7
create a 0.9V termination voltage at V
Characteristics Table for exact values of V
ture).
V
The purpose of the sense pin is to provide improved remote
load regulation. In most motherboard applications the termi-
nation resistors will connect to V
output voltage was regulated only at the output of the
LP2997 then the long trace will cause a significant IR drop
resulting in a termination voltage lower at one end of the bus
than the other. The V
performance, by connecting it to the middle of the bus. This
will provide a better distribution across the entire termination
bus. If remote load regulation is not used then the V
pin must still be connected to V
when a long V
to the memory. Noise pickup in the V
problems with precise regulation of V
ramic capacitor placed next to the V
any high frequency signals and preventing errors.
SHUTDOWN
The LP2997 contains an active low shutdown pin that can be
used for suspend to RAM functionality. In this condition the
V
providing a constant reference signal for the memory and
chipset. During shutdown V
voltages that exceed PVIN. With the shutdown pin asserted
low the quiescent current of the LP2997 will drop, however,
VDDQ will always maintain its constant impedance of 100kΩ
for generating the internal reference. Therefore, to calculate
the total power loss in shutdown both currents need to be
considered. For more information refer to the Thermal Dis-
sipation section. The shutdown pin also has an internal
pull-up current; therefore, to turn the part on the shutdown
pin can either be connected to AVIN or left open
V
V
voltage VDDQ / 2. This output should be used to provide the
reference voltage for the Northbridge chipset and memory.
Since these inputs are typically an extremely high imped-
ance, there should be little current drawn from V
improved performance, an output bypass capacitor can be
used, located close to the pin, to help with noise. A ceramic
capacitor in the range of 0.1 µF to 0.01 µF is recommended.
SENSE
TT
REF
REF
output will tri-state while the V
provides the buffered output of the internal reference
SENSE
trace is implemented in close proximity
SENSE
pin can be used to improve this
TT
20109405
should not be exposed to
TT
TT
REF
. Care should be taken
SENSE
SENSE
in a long plane. If the
TT
output remains active
. A small 0.1uF ce-
TT
pin can help filter
TT
trace can cause
(See Electrical
over tempera-
www.national.com
REF
SENSE
. For