SAF-C505-2RM Siemens Semiconductor Group, SAF-C505-2RM Datasheet - Page 37
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SAF-C505-2RM
Manufacturer Part Number
SAF-C505-2RM
Description
8-Bit CMOS Microcontroller
Manufacturer
Siemens Semiconductor Group
Datasheet
1.SAF-C505-2RM.pdf
(85 pages)
- Current page: 37 of 85
- Download datasheet (336Kb)
C505 / C505C
C505A / C505CA
CAN Controller (C505C and C505CA only)
The on-chip CAN controller, compliant to version 2.0B, is the functional heart which provides all
resources that are required to run the standard CAN protocol (11-bit identifiers) as well as the
extended CAN protocol (29-bit identifiers). It provides a sophisticated object layer to relieve the
CPU of as much overhead as possible when controlling many different message objects (up to 15).
This includes bus arbitration, resending of garbled messages, error handling, interrupt generation,
etc. In order to implement the physical layer, external components have to be connected to the
C505.
The internal bus interface connects the on-chip CAN controller to the internal bus of the
microcontroller. The registers and data locations of the CAN interface are mapped to a specific
256 byte wide address range of the external data memory area (F700 H to F7FF H ) and can be
accessed using MOVX instructions. Figure 15 shows a block diagram of the on-chip CAN
controller.
TXDC
RXDC
Bit
BTL-Configuration
Timing
Logic
CRC
Timing
Gen./Check
Generator
TX/RX Shift Register
Messages
Clocks
Messages
Intelligent
(to all)
Handlers
Memory
Control
Interrupt
Register
Status +
Bit
Control
Stream
Processor
Error
Management
Status
Logic
Register
to internal Bus
MCB02736
Figure 15
CAN Controller Block Diagram
Semiconductor Group
37
1997-12-01
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