ADG511 Analog Devices, ADG511 Datasheet - Page 8

• Manufacturer Part Number: ADG511
• Description: LC2MOS Precision 5 V/3 V Quad SPST Switches
• Manufacturer: Analog Devices

APPLICATION
Figure 9 illustrates a precise sample-and-hold circuit. An AD845
is used as the input buffer while the output operational amplifier
is an OP07. During the track mode, SW1 is closed and the
output V
SW1 is opened and the signal is held by the hold capacitor C
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG511/ADG512/
ADG513 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a poly-
styrene hold capacitor. The droop rate for the circuit shown is
typically 15 V/ s.
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp OP07, which will minimize charge
injection effects. Pedestal error is also reduced by the compensation
ADG511/ADG512/ADG513
Figure 7. Leakage Currents as a Function of V
–0.002
–0.004
–0.006
0.008
0.004
0.002
0.000
110
100
90
80
70
60
OUT
–5
100
follows the input signal V
Figure 8. Crosstalk vs. Frequency
V
V
T
–4
A
DD
SS
= +25 C
V
= –5V
= +5V
D
–3
OR V
1k
S
–2
– DRAIN OR SOURCE VOLTAGE – V
FREQUENCY – Hz
–1
10k
0
I
100k
D
1
(ON)
IN
. In the hold mode,
2
V
V
DD
SS
3
1M
I
I
D
S
= –5V
= +5V
(OFF)
(OFF)
4
D
10M
5
(V
S
)
H
.
–8–
network R
the hold time glitch while optimizing the acquisition time. Using
the illustrated op amps and component values, the pedestal
error has a maximum value of 5 mV over the 3 V input range.
The acquisition time is 2.5 s while the settling time is 1.85 s.
TRENCH ISOLATION
The MOS devices that make up the ADG511A/ADG512A/
ADG513A are isolated from each other by an oxide layer
(trench) (see Figure 10). When the NMOS and PMOS devices
are not electrically isolated from each other, there exists the
possibility of “latch-up” caused by parasitic junctions between
CMOS transistors. Latch-up is caused when P-N junctions that
are normally reverse biased, become forward biased, causing
large currents to flow. This can be destructive.
CMOS devices are normally isolated from each other by
Junction Isolation. In Junction Isolation the N and P wells of the
CMOS transistors form a diode that is reverse biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward biased. A Silicon-Controlled Rectifier
(SCR)-type circuit is formed by the two transistors, causing a
significant amplification of the current that, in turn, leads to
latch-up. With Trench Isolation, this diode is removed; the
result is a latch-up-proof circuit.
V
IN
AD845
T
R
E
N
C
H
+5V
–5V
C
Figure 9. Accurate Sample-and-Hold
V
and C
P
N
S
+
–
P-CHANNEL
Figure 10. Trench Isolation
C
V
. This compensation network also reduces
S
S
G
SW2
SW1
SUBSTRATE (BACKGATE)
BURIED OXIDE LAYER
+5V
ADG511
ADG512
ADG513
V
P
D
+
–5V
T
R
E
N
C
H
D
D
75
R
V
2200pF
C
N
P
2200pF
S
+
–
C
1000pF
C
C
N-CHANNEL
H
V
G
OP07
+5V
–5V
V
N
D
+
T
R
E
N
C
H
REV. B
V
OUT