SAK-C164CI-8RM Infineon Technologies AG, SAK-C164CI-8RM Datasheet - Page 62
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SAK-C164CI-8RM
Manufacturer Part Number
SAK-C164CI-8RM
Description
16-Bit Single-Chip Microcontroller
Manufacturer
Infineon Technologies AG
Datasheets
1.SAK-C164CI-8RM.pdf
(79 pages)
2.SAK-C164SL-6RM.pdf
(79 pages)
3.SAK-C164CL-8R25M.pdf
(79 pages)
- Current page: 62 of 79
- Download datasheet (2Mb)
Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
The following table describes, how these variables are to be computed.
Table 15
Description
ALE Extension
Memory Cycle Time Waitstates
Memory Tristate Time
Note: Please respect the maximum operating frequency of the respective derivative.
AC Characteristics
Multiplexed Bus
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
Parameter
ALE high time
Address setup to ALE
Address hold after ALE
ALE falling edge to RD,
WR (with RW-delay)
ALE falling edge to RD,
WR (no RW-delay)
Address float after RD,
WR (with RW-delay)
Address float after RD,
WR (no RW-delay)
RD, WR low time
(with RW-delay)
Data Sheet
Memory Cycle Variables
t
Symbol
t
t
t
t
t
t
t
t
A
5
6
7
8
9
10
11
12
+
t
CC 10 +
CC 4 +
CC 10 +
CC 10 +
CC -10 +
CC –
CC –
CC 30 +
C
+
Symbol
t
t
t
A
C
F
t
F
min.
Max. CPU Clock
(120 ns at 25 MHz CPU clock without waitstates)
t
= 25 MHz
A
t
t
t
t
58
A
A
A
C
t
A
Values
TCL × <ALECTL>
2TCL × (15 - <MCTC>)
2TCL × (1 - <MTTC>)
max.
–
–
–
–
–
6
26
–
1 / 2TCL = 1 to 25 MHz
min.
TCL - 10
+
TCL - 16
+
TCL - 10
+
TCL - 10
+
-10 +
–
–
2TCL - 10
+
Variable CPU Clock
t
t
t
t
t
A
A
A
A
C
t
A
max.
–
–
–
–
–
6
TCL + 6
–
C164CL/SL
V2.0, 2001-05
C164CI/SI
Unit
ns
ns
ns
ns
ns
ns
ns
ns
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