PXB4220E Infineon Technologies AG, PXB4220E Datasheet - Page 146

• Manufacturer Part Number: PXB4220E
• Description: Interworking Element for 8 E1/T1 Lines
• Manufacturer: Infineon Technologies AG

RMADR
MPADR
6.2.7.1
The SW does not need to access the ATM Receive Buffers.
6.2.7.2
The ATM header to be used for each channel has to be programmed at the address
given by:
RMADR
MPADR
All other locations should never be accessed as the data changes continuously.
The format of the ATM header entry in the cell insertion buffer is as follows:
6.2.8
Read/write Address 30000
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size 32K
Data Sheet
31
23
15
7
GFC[3:0] or VPI[11:8]
17 16 15 14 13 12 11 10 9
ATM Receive Buffer
Segmentation Buffer
17 16 15 14 13 12 11 10 9
Reassembly/ATM Transmit Buffers
1
1
15 14 13 12 11 10 9
15 14 13 12 11 10 9
0
0
VCI[3:0]
VPI[3:0]
32 bits: 8 ports x 32 channels x 8 cells x 16 doublewords
1
1 port_nr[2:0]
port_nr
[2:0]
H
to 3FFFF
VCI[11:4]
ref_slot_nr[4:0]
H
channel_nr
146
[4:0]
PXB 4219E, PXB 4220E, PXB 4221E
8
8
7
8
7
8
6
7
6
7
PTI[2:0]
cell_nr
5
6
5
6
[1:0]
00
VCI[15:12]
VPI[7:4]
B
4
5
4
5
3
4
3
4
Memory Structure
double_word
0000
2
3
2
3
[3:0]
IWE8, V3.4
1
2
1
2
B
2003-01-20
CLP
0
1
0
1
24
16
8
0
0
0
0
0