AT89S52-33AC ATMEL Corporation, AT89S52-33AC Datasheet - Page 16

• Manufacturer Part Number: AT89S52-33AC
• Description: 8-bit Microcontroller with 8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Program Memory Lock Bits
The AT89S52 has three lock bits that can be left unpro-
grammed (U) or can be programmed (P) to obtain the addi-
tional features listed in the following table.
Table 7. Lock Bit Protection Modes
When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during reset. If the device is pow-
ered up without a reset, the latch initializes to a random
value and holds that value until reset is activated. The
latched value of EA must agree with the current logic level
at that pin in order for the device to function properly.
Programming the Flash – Parallel Mode
The AT89S52 is shipped with the on-chip Flash memory
array ready to be programmed. The programming interface
needs a high-voltage (12-volt) program enable signal and
is compatible with conventional third-party Flash or
EPROM programmers.
The AT89S52 code memory array is programmed byte-by-
byte.
Programming Algorithm: Before programming the
AT89S52, the address, data, and control signals should be
set up according to the Flash programming mode table and
Figures 13 and 14. To program the AT89S52, take the fol-
lowing steps:
1. Input the desired memory location on the address
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/V
5. Pulse ALE/PROG once to program a byte in the
16
1
2
3
4
lines.
Flash array or the lock bits. The byte-write cycle is
self-timed and typically takes no more than 50 µs.
Program Lock Bits
LB1
U
P
P
P
PP
LB2
U
U
P
P
to 12V.
LB3
U
U
U
P
AT89S52
Protection Type
No program lock features
MOVC instructions executed
from external program
memory are disabled from
fetching code bytes from
internal memory, EA is
sampled and latched on reset,
and further programming of
the Flash memory is disabled
Same as mode 2, but verify is
also disabled
Same as mode 3, but external
execution is also disabled
Data Polling: The AT89S52 features Data Polling to indi-
cate the end of a byte write cycle. During a write cycle, an
attempted read of the last byte written will result in the com-
plement of the written data on P0.7. Once the write cycle
has been completed, true data is valid on all outputs, and
the next cycle may begin. Data Polling may begin any time
after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can also
be monitored by the RDY/BSY output signal. P3.0 is pulled
low after ALE goes high during programming to indicate
BUSY. P3.0 is pulled high again when programming is
done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been
programmed, the programmed code data can be read back
via the address and data lines for verification. The status of
the individual lock bits can be verified directly by reading
them back.
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of
locations 000H, 100H, and 200H, except that P3.6 and
P3.7 must be pulled to a logic low. The values returned are
as follows.
Chip Erase: In the parallel programming mode, a chip
erase operation is initiated by using the proper combination
of control signals and by pulsing ALE/PROG low for a dura-
tion of 200 ns - 500 ns.
In the serial programming mode, a chip erase operation is
initiated by issuing the Chip Erase instruction. In this mode,
chip erase is self-timed and takes about 500 ms.
During chip erase, a serial read from any address location
will return 00H at the data output.
Programming the Flash – Serial Mode
The Code memory array can be programmed using the
serial ISP interface while RST is pulled to V
interface consists of pins SCK, MOSI (input) and MISO
(output). After RST is set high, the Programming Enable
instruction needs to be executed first before other opera-
tions can be executed. Before a reprogramming sequence
can occur, a Chip Erase operation is required.
The Chip Erase operation turns the content of every mem-
ory location in the Code array into FFH.
Either an external system clock can be supplied at pin
XTAL1 or a crystal needs to be connected across pins
XTAL1 and XTAL2. The maximum serial clock (SCK)
Repeat steps 1 through 5, changing the address
and data for the entire array or until the end of the
object file is reached.
(000H) = 1EH indicates manufactured by Atmel
(100H) = 52H indicates 89S52
(200H) = 06H
CC
. The serial