AT89S52-33AC ATMEL Corporation, AT89S52-33AC Datasheet

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AT89S52-33AC

Manufacturer Part Number
AT89S52-33AC
Description
8-bit Microcontroller with 8K Bytes In-System Programmable Flash
Manufacturer
ATMEL Corporation
Datasheet

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AT89S52-33AC
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Features
Description
The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K
bytes of in-system programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the indus-
try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-
grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on
a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a
highly-flexible and cost-effective solution to many embedded control applications.
The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes
of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a
six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,
and clock circuitry. In addition, the AT89S52 is designed with static logic for operation
down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and
interrupt system to continue functioning. The Power-down mode saves the RAM con-
tents but freezes the oscillator, disabling all other chip functions until the next interrupt
or hardware reset.
Compatible with MCS-51
8K Bytes of In-System Programmable (ISP) Flash Memory
4.0V to 5.5V Operating Range
Fully Static Operation: 0 Hz to 33 MHz
Three-level Program Memory Lock
256 x 8-bit Internal RAM
32 Programmable I/O Lines
Three 16-bit Timer/Counters
Eight Interrupt Sources
Full Duplex UART Serial Channel
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Watchdog Timer
Dual Data Pointer
Power-off Flag
– Endurance: 1000 Write/Erase Cycles
®
Products
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
AT89S52
Rev. 1919A-07/01
1

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AT89S52-33AC Summary of contents

Page 1

... RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. ...

Page 2

... XTAL2 18 23 P2.2 (A10) XTAL1 19 22 P2.1 (A9) GND 20 21 P2.0 (A8) TQFP (MOSI) P1.5 1 (MISO) P1.6 2 (SCK) P1.7 3 RST 4 (RXD) P3 (TXD) P3.1 7 (INT0) P3.2 8 (INT1) P3.3 9 (T0) P3.4 10 (T1) P3.5 11 AT89S52 2 (MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 33 P0.4 (AD4) 32 P0.5 (AD5) 31 P0.6 (AD6) 30 P0.7 (AD7) 29 EA/VPP ALE/PROG 26 PSEN 25 P2.7 (A15) 24 P2.6 (A14) 23 P2.5 (A13) PLCC ...

Page 3

Block Diagram V CC GND RAM ADDR. REGISTER B REGISTER PSEN TIMING ALE/PROG INSTRUCTION AND REGISTER CONTROL RST WATCH DOG OSC P0.0 - P0.7 PORT 0 DRIVERS PORT 0 PORT 2 RAM LATCH ACC TMP2 TMP1 ...

Page 4

... Port 3 pins that are externally being pulled low will source current (I ) because of the pullups. IL Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table. Port 3 also receives some control signals for Flash pro- gramming and verification. Port Pin Alternate Functions P3 ...

Page 5

... PSEN Program Store Enable (PSEN) is the read strobe to exter- nal program memory. When the AT89S52 is executing code from external pro- gram memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. ...

Page 6

... Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. AT89S52 6 new features. In that case, the reset or inactive values of the new bits will always be 0 ...

Page 7

Table 3a. AUXR: Auxiliary Register AUXR Address = 8EH Not Bit Addressable – Bit 7 – Reserved for future expansion DISALE Disable/Enable ALE DISALE Operating Mode 0 ALE is emitted at a constant rate of 1/6 the oscillator frequency 1 ...

Page 8

... Program and Data Memory can be addressed. Program Memory If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52 connected to V fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory. ...

Page 9

... Flash Microcontroller’, then ‘Product Overview’. Timer 0 and 1 Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers’ operation, refer to the ATMEL Web site (http://www.atmel.com). From the home page, select ‘ ...

Page 10

... TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 6. In this mode, the T2EX pin controls AT89S52 10 This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1- ...

Page 11

Figure 6. Timer 2 Auto Reload Mode (DCEN = 0) ÷12 OSC T2 PIN TRANSITION DETECTOR T2EX PIN Table 4. T2MOD – Timer 2 Mode Control Register T2MOD Address = 0C9H Not Bit Addressable – – Bit 7 6 Symbol ...

Page 12

... C/ PIN Figure 8. Timer 2 in Baud Rate Generator Mode NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12 ÷ 2 OSC C/ C/ PIN TRANSITION DETECTOR T2EX PIN AT89S52 12 (DOWN COUNTING RELOAD VALUE) 0FFH 0FFH OVERFLOW TH2 TL2 CONTROL TR2 RCAP2H RCAP2L (UP COUNTING RELOAD VALUE) TH2 ...

Page 13

Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the ...

Page 14

... RCAP2H and RCAP2L. Interrupts The AT89S52 has a total of six interrupt vectors: two exter- nal interrupts (INT0 and INT1), three timer interrupts (Tim- ers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10 ...

Page 15

Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 11. Either a quartz crystal or ceramic resonator may be used. ...

Page 16

... Program Memory Lock Bits The AT89S52 has three lock bits that can be left unpro- grammed (U) or can be programmed (P) to obtain the addi- tional features listed in the following table. Table 7. Lock Bit Protection Modes Program Lock Bits LB1 LB2 LB3 Protection Type ...

Page 17

... With a 33 MHz oscillator clock, the maximum SCK frequency is 2 MHz. Serial Programming Algorithm To program and verify the AT89S52 in the serial program- ming mode, the following sequence is recommended: 1. Power-up sequence: Apply power between VCC and GND pins. ...

Page 18

... H D OUT P0. P0.3, P0 1EH 52H 06H AT89S52 ADDR. P1.0-P1.7 CC 0000H/1FFFH P0 P2 A12 P2.6 P2.7 ALE SEE FLASH P3.3 PROGRAMMING MODES TABLE P3.6 P3.7 XTAL 2 EA 3-33 MHz XTAL1 RST GND PSEN P2.4-0 P1.7-0 Address A12-8 A7-0 A12-8 A7 ...

Page 19

Flash Programming and Verification Characteristics (Parallel Mode 20°C to 30° 4 Symbol Parameter V Programming Supply Voltage PP I Programming Supply Current Supply Current CC CC 1/t Oscillator Frequency ...

Page 20

... Figure 16. Flash Memory Serial Downloading Flash Programming and Verification Waveforms – Serial Mode Figure 17. Serial Programming Waveforms AT89S52 20 AT89S52 INSTRUCTION P1.5/MOSI INPUT P1.6/MISO DATA OUTPUT P1.7/SCK CLOCK IN XTAL2 3-33 MHz XTAL1 GND RST ...

Page 21

Table 9. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Programming Enable 1010 1100 Chip Erase 1010 1100 Read Program Memory 0010 0000 (Byte Mode) Write Program Memory 0100 0000 (Byte Mode) (2) Write Lock Bits 1010 1100 Read ...

Page 22

... MOSI Setup to SCK High OVSH t MOSI Hold after SCK High SHOX t SCK Low to MISO Valid SLIV t Chip Erase Instruction Cycle Time ERASE t Serial Byte Write Cycle Time SWC AT89S52 OVSH SHOX SCK t SHSL = - Min CLCL ...

Page 23

Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage ............................................ 6.6V DC Output Current...................................................... 15 Characteristics The values shown ...

Page 24

... Address Low AVWL t Data Valid to WR Transition QVWX t Data Valid to WR High QVWH t Data Hold After WR WHQX t RD Low to Address Float RLAZ High to ALE High WHLH AT89S52 24 12 MHz Oscillator Variable Oscillator Min Max Min 0 127 2t -40 CLCL 43 t -25 CLCL 48 ...

Page 25

External Program Memory Read Cycle ALE PSEN PORT 0 PORT 2 External Data Memory Read Cycle ALE PSEN RD PORT 0 PORT 2 t LHLL t AVLL t LLPL t PLAZ t LLAX AVIV A8 - ...

Page 26

... External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL AT89S52 26 t LHLL t t LLWL WLWH t LLAX t t QVWX AVLL t QVWH DATA OUT t AVWL P2 A15 FROM DPH t ...

Page 27

Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for V Symbol Parameter t Serial Port Clock Cycle Time XLXL t Output Data Setup to Clock Rising Edge QVXH t Output Data Hold After ...

Page 28

... Ordering Code 24 4.0V to 5.5V AT89S52-24AC AT89S52-24JC AT89S52-24PC AT89S52-24AI AT89S52-24JI AT89S52-24PI 33 4.5V to 5.5V AT89S52-33AC AT89S52-33JC AT89S52-33PC = Preliminary Availability 44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) AT89S52 ...

Page 29

... MAX SEATING PLANE .161(4.09) .125(3.18) .065(1.65) .110(2.79) .041(1.04) .090(2.29) .630(16.0) .590(15.0) .012(.305) .008(.203) .690(17.5) .610(15.5) AT89S52 29 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) 12.21(0.478) SQ 11.75(0.458) 0.45(0.018) .032(.813) 0.30(0.012) .026(.660) .050(1.27) TYP 10.10(0.394) SQ 9.90(0.386) 1 ...

Page 30

... Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...

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