AT89S51-24SC ATMEL Corporation, AT89S51-24SC Datasheet - Page 13

• Manufacturer Part Number: AT89S51-24SC
• Description: 8-bit Microcontroller with 4K Bytes In-System Programmable Flash
• Manufacturer: ATMEL Corporation

Programming
the Flash –
Serial Mode
Serial
Programming
Algorithm
2487B–MICRO–12/03
Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY out-
put signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0
is pulled high again when programming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code
data can be read back via the address and data lines for verification. The status of the indi-
vidual lock bits can be verified directly by reading them back.
Reading the Signature Bytes: The signature bytes are read by the same procedure as a nor-
mal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled
to a logic low. The values returned are as follows.
Chip Erase: In the parallel programming mode, a chip erase operation is initiated by using the
proper combination of control signals and by pulsing ALE/PROG low for a duration of 200 ns -
500 ns.
In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase
instruction. In this mode, chip erase is self-timed and takes about 500 ms.
During chip erase, a serial read from any address location will return 00H at the data output.
The Code memory array can be programmed using the serial ISP interface while RST is
pulled to V
RST is set high, the Programming Enable instruction needs to be executed first before other
operations can be executed. Before a reprogramming sequence can occur, a Chip Erase
operation is required.
The Chip Erase operation turns the content of every memory location in the Code array into
FFH.
Either an external system clock can be supplied at pin XTAL1 or a crystal needs to be con-
nected across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be
less than 1/16 of the crystal frequency. With a 33 MHz oscillator clock, the maximum SCK fre-
quency is 2 MHz.
To program and verify the AT89S51 in the serial programming mode, the following sequence
is recommended:
1. Power-up sequence:
2. Enable serial programming by sending the Programming Enable serial instruction to
3. The Code array is programmed one byte at a time in either the Byte or Page mode. The
4. Any memory location can be verified by using the Read instruction that returns the con-
5. At the end of a programming session, RST can be set low to commence normal device
Apply power between VCC and GND pins.
Set RST pin to “H”.
If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 33 MHz
clock to XTAL1 pin and wait for at least 10 milliseconds.
pin MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be
less than the CPU clock at XTAL1 divided by 16.
write cycle is self-timed and typically takes less than 0.5 ms at 5V.
tent at the selected address at serial output MISO/P1.6.
operation.
(000H) = 1EH indicates manufactured by Atmel
(100H) = 51H indicates AT89S51
(200H) = 06H
CC
. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After
AT89S51
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