A29L400UV-90U AMICC [AMIC Technology], A29L400UV-90U Datasheet

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A29L400UV-90U

Manufacturer Part Number
A29L400UV-90U
Description
512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
Manufacturer
AMICC [AMIC Technology]
Datasheet
Preliminary
Features
n Single power supply operation
n Access times:
n Current:
n Flexible sector architecture
n Extended operating temperature range: -45 C ~ +85 C
n Unlock Bypass Program Command
n Top or bottom boot block configurations available
n Embedded Algorithms
PRELIMINARY
- Embedded Program algorithm automatically writes
- 200 nA typical CMOS standby
- 200 nA Automatic Sleep Mode current
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX7 sectors
- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX7 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
for –U series
- Full voltage range: 2.7 to 3.6 volt read and write
- Regulated voltage range: 3.0 to 3.6 volt read and write
- 70/90 (max.)
- 4 mA typical active read current
- 20 mA typical program/erase current
- Reduces overall programming time when issuing
- Embedded Erase algorithm will automatically erase
operations for battery-powered applications
operations for compatibility with high performance 3.3
volt microprocessors
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector. Temporary Sector Unprotect feature
allows code changes in previously locked sectors
multiple program command sequence
the entire chip or any combination of designated
sectors and verify the erased sectors
and verifies data at specified addresses
(October, 2002, Version 0.2)
512K X 8 Bit / 256K X 16 Bit CMOS 3.0 Volt-only,
1
n Typical 100,000 program/erase cycles per sector
n 20-year data retention at 125 C
n Compatible with JEDEC-standards
n
n Ready /
n Erase Suspend/Erase Resume
n Hardware reset pin (
n Package options
- Reliable operation for the life of the system
- Pinout and software compatible with single-power-
- Superior inadvertent write protection
- Provides a software method of detecting completion
- Provides a hardware method of detecting completion
- Suspends a sector erase operation to read data from,
- Hardware method to reset the device to reading array
- 44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA
Data
supply Flash memory standard
of program or erase operations (not available on 44-
pin SOP)
data
of program or erase operations
or program data to, a non-erasing sector, then
resumes the erase operation
Polling and toggle bits
Boot Sector Flash Memory
BUSY
pin (RY /
A29L400 Series
RESET
AMIC Technology, Inc.
BY
)
)

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A29L400UV-90U Summary of contents

Page 1

Preliminary Features n Single power supply operation - Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications - Regulated voltage range: 3.0 to 3.6 volt read and write operations for compatibility with high performance 3.3 ...

Page 2

General Description The A29L400 is an 4Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes of 8 bits or 262,144 words of 16 bits each. The 8 bits of data appear on I/O of data appear on I/O ~I/O . ...

Page 3

Pin Configurations n SOP NC 1 RESET RY/BY A17 A10 A11 A12 A13 37 A2 A14 9 36 ...

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Block Diagram RY/BY VCC VSS RESET State WE Control BYTE Command Register CE OE VCC Detector A0-A17 Pin Descriptions A0 - A17 I/O I/O (A-1) 15 RESET PRELIMINARY (October, 2002, Version 0.2) Sector Switches Erase Voltage Generator PGM Voltage Generator ...

Page 5

Absolute Maximum Ratings* Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 6

Word/Byte Configuration The BYTE pin determines whether the I/O pins I/O operate in the byte or word configuration. If the is set at logic ”1”, the device is in word configuration, I/O I/O are active and controlled ...

Page 7

Output Disable Mode When the OE input output from the device is IH disabled. The output pins are placed in the high impedance state. RESET : Hardware Reset Pin The RESET pin provides a hardware method ...

Page 8

Table 2. A29L400 Top Boot Block Sector Address Table Sector A17 A16 A15 SA0 SA1 SA2 SA3 SA4 SA5 SA6 1 1 ...

Page 9

Table 4. A29L400 Autoselect Codes (High Voltage Method) Description Mode CE Manufacturer ID: AMIC L Device ID: Word A29L400 L Byte (Top Boot Block) Device ID: Word A29L400 L Byte (Bottom Boot Block) Continuation ID L Sector Protection Verification L ...

Page 10

Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors possible to determine whether a sector is ...

Page 11

START PLSCNT=1 RESET=V ID Wait Temporary Sector First Write Unprotect Mode Cycle=60h? Yes Set up sector address Sector Protect Write 60h to sector address with A6=0, A1=1, A0=0 Wait 150 us Verify Sector Protect: Write 40h to ...

Page 12

Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence ...

Page 13

START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data ? Increment Address Last Address ? Programming Completed Note : See the appropriate Command Definitions table for program command sequence. Figure 3. Program Operation ...

Page 14

Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor I/O . Any command other than Sector ...

Page 15

Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Word Manufacturer ID 4 Byte Word Device ID, 4 Byte Top Boot Block Word Device ID, 4 Bottom Boot Block Byte Word Continuation ID 4 Byte Word Sector ...

Page 16

Note: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operation. 4. Data bits I/O ~I/O are don’t care for unlock ...

Page 17

Write Operation Status Several bits, I/O , I/O , I/O , I the A29L400 to determine the status of a write operation. Table 6 and the following subsections describe the functions of these ...

Page 18

BY : Read/ Busy RY/ The RY dedicated, open-drain output pin that indicates whether an Embedded algorithm is in progress or complete. The RY/ BY status is valid after the rising edge of the final WE pulse ...

Page 19

I/O : Exceeded Timing Limits 5 I/O indicates whether the program or erase time has 5 exceeded a specified internal pulse count limit. Under these conditions I/O produces a "1." This is a failure condition 5 that indicates the program ...

Page 20

Operation Standard Embedded Program Algorithm Mode Embedded Erase Algorithm Erase Reading within Erase Suspend Suspended Sector Mode Reading within Non-Erase Suspended Sector Erase-Suspend-Program Notes: 1. I/O and I/O require a valid address when reading status information. Refer to the appropriate ...

Page 21

DC Characteristics CMOS Compatible ( - + Parameter Parameter Description Symbol I Input Load Current Input Load Current LIT I Output Leakage Current LO VCC Active Read ...

Page 22

DC Characteristics (continued) Zero Power Flash 500 1000 Note: Addresses are switching at 1MHz I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note ...

Page 23

AC Characteristics Read Only Operations ( - + Parameter Symbols JEDEC Std Read Cycle Time (Note AVAV RC Address to Output Delay t t AVQV ACC Chip ...

Page 24

AC Characteristics Hardware Reset ( RESET ) ( - + Parameter JEDEC Std RESET Pin Low (During Embedded t READY Algorithms) to Read or Write (See Note) RESET Pin Low ...

Page 25

Temporary Sector Unprotect (T A Parameter JEDEC Std t V Rise and Fall Time (See Note) VIDR ID RESET Setup Time for Temporary Sector t RSP Unprotect Note: Not 100% tested. Temporary Sector Unprotect Timing Diagram 12V ...

Page 26

AC Characteristics Word/Byte Configuration ( BYTE ) (T Parameter JEDEC Std t t ELFL/ ELFH CE BYTE to BYTE Switching Low to Output High-Z t FLQZ BYTE Switching High to Output Active t HQV BYTE Timings for Read Operations CE ...

Page 27

AC Characteristics Erase and Program Operations (T A Parameter JEDEC Std t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH ...

Page 28

Timing Waveforms for Program Operation Program Command Sequence (last two cycles Addresses 555h Data RY/BY t VCS VCC Note : program addrss program data, Dout is the true ...

Page 29

Timing Waveforms for Chip/Sector Erase Operation Erase Command Sequence (last two cycles Addresses 2AAh Data RY/BY t VCS VCC Note : Sector Address (for Sector Erase Valid Address ...

Page 30

Timing Waveforms for Data Polling (During Embedded Algorithms Addresses VA t ACC OEH WE I/O 7 I/O - I/O High BUSY RY/BY Note : VA = Valid Address. ...

Page 31

Timing Waveforms for Toggle Bit (During Embedded Algorithms Addresses VA t ACC OEH WE I/O , I/O High BUSY RY/BY Note Valid Address; not required for ...

Page 32

Timing Waveforms for Sector Protect/Unprotect RESET SA, A6, A1, A0 Sector Protect/Unprotect 60h Data 1us Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0 PRELIMINARY (October, 2002, Version ...

Page 33

Timing Waveforms for I/O vs. I/O 2 Enter Erase Embedded Suspend Erasing WE Erase Erase Suspend I/O 6 I/O 2 I/O and I/O toggle with OE and Note : Both I/O and I/O toggle with OE or ...

Page 34

Timing Waveforms for Alternate CE Controlled Write Operation 555 for program 2AA for erase Addresses Data for program 55 for erase RESET RY/BY Note : 1. ...

Page 35

Latch-up Characteristics Input Voltage with respect to VSS on all I/O pins VCC Current Input voltage with respect to VSS on all pins except I/O pins (including A9, OE and RESET ) Includes all pins except VCC. Test conditions: VCC ...

Page 36

Test Conditions Test Specifications Test Condition Output Load Output Load Capacitance, C (including jig capacitance) L Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Test Setup Device Under Test PRELIMINARY ...

Page 37

... A29L400TV-70 70 A29L400TG-70 A29L400TM-90 A29L400TV-90 A29L400TV-90U 90 A29L400TG-90 A29L400TG-90U Bottom Boot Sector Flash Access Time Part No. (ns) A29L400UM-70 A29L400UV-70 70 A29L400UG-70 A29L400UM-90 A29L400UV-90 A29L400UV-90U 90 A29L400UG-90 A29L400UG-90U PRELIMINARY (October, 2002, Version 0.2) Active Read Program/Erase Current Current Typ. (mA) Typ. (mA Active Read Program/Erase Current Current Typ ...

Page 38

Package Information SOP 44L Outline Dimensions Seating Plane Symbol Notes: 1. The maximum value of dimension D includes ...

Page 39

Package Information TSOP 48L (Type I) Outline Dimensions 1 24 Detail "A" Symbol Notes: 1. The maximum value of dimension D includes end flash. 2. ...

Page 40

Package Information 48LD CSP ( mm) Outline Dimensions (48TFBGA Ball*A1 CORNER C 0.10 C PRELIMINARY (October, 2002, Version 0.2) TOP VIEW BOTTOM VIEW b ...

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