A29L160TG-120 AMICC [AMIC Technology], A29L160TG-120 Datasheet - Page 7

• Manufacturer Part Number: A29L160TG-120
• Description: 2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
• Manufacturer: AMICC [AMIC Technology]

Word/Byte Configuration
The
operate in the byte or word configuration. If the
is set at logic ”1”, the device is in word configuration, I/O
I/O
If the
configuration, and only I/O
by
used as an input for the LSB(A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the
selects the device.
array data to the output pins.
the time during read operation. The
whether the device outputs array data in words and bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content
occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses on
the device address inputs produce valid data on the device
data outputs. The device remains enabled for read access
until the command register contents are altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to
the Read Operations Timings diagram for the timing
waveforms, l
the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive
V
determines whether the device accepts program data in
bytes or words, Refer to “Word/Byte Configuration” for more
information. The device features an Unlock Bypass mode to
facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to
program a word or byte, instead of four. The “
Word / Byte Program Command Sequence” section has
details on programming data to the device using both
standard and Unlock Bypass command sequence. An
erase operation can erase one sector, multiple sectors, or
the entire device. The Sector Address Tables indicate the
address range that each sector occupies. A "sector
address" consists of the address inputs required to uniquely
PRELIMINARY
IL
, and
0
CE
CE
are active and controlled by
BYTE
BYTE
and
and
OE
pin determines whether the I/O pins I/O
OE
OE
CC1
to V
pin is set at logic “0”, the device is in byte
. I/O
in the DC Characteristics table represents
pins to V
IH
(July, 2002, Version 0.0)
. For program operations, the
OE
8
-I/O
14
is the output control and gates
IL
0
.
-I/O
are tri-stated, and I/O
CE
WE
7
CE
are active and controlled
is the power control and
should remain at V
and
BYTE
OE
WE
pin determines
.
and
BYTE
BYTE
15
15
CE
pin is
-I/O
IH
pin
pin
15
all
to
0
-
6
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for t
automatic sleep mode is independent of the
provide new data when addresses are changed. While in
sleep mode, output data is latched and always available to
the system. I
the automatic sleep mode current specification.
select a sector. See the "Command Definitions" section for
details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can
then read autoselect codes from the internal register (which
is separate from the memory array) on I/O
read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
I
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section
for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the
input.
The device enters the CMOS standby mode when the
& RESET pins are both held at VCC
is a more restricted voltage range than V
device will be in the standby mode, but the standby current
will be greater. The device requires the standard access
time (t
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
I
standby current specification.
Automatic Sleep Mode
OE
RESET are held at V
CC2
CC3
and I
in the DC Characteristics table represents the active
control signals. Standard address access timings
CE
7
) before it is ready to read data.
- I/O
CC4
in the DC Characteristics tables represent the
CC4
0
. Standard read cycle timings and I
in the DC Characteristics table represents
IH
, but not within VCC
AMIC Technology, Inc.
A29L160 Series
0.3V. (Note that this
ACC
7
- I/O
IH
.) If
CE
+30ns. The
0
. Standard
0.3V, the
,
WE
CE
CC
read
OE
CE
and
and