A29L040A-70 AMICC [AMIC Technology], A29L040A-70 Datasheet - Page 2

• Manufacturer Part Number: A29L040A-70
• Description: 512K X 8 Bit CMOS 3.0 Volt-only, Uniform Sector Flash Memory
• Manufacturer: AMICC [AMIC Technology]

Preliminary
Features
General Description
The A29L040A is entirely software command set compatible
with the JEDEC single-power-supply
PRELIMINARY
The A29L040A is a 3.0 volt-only Flash memory organized as
524,288 bytes of 8 bits each. The 512 Kbytes of data are
further divided into eight sectors of 64 Kbytes each for
flexible sector erase capability. The 8 bits of data appear on
I/O
A29L040A is offered in 32-pin PLCC, TSOP (8mm x 20mm)
or sTSOP (8mm x 13.4mm) packages. This device is
designed to be programmed in-system with the standard
system 3.0 volt VCC supply. Additional 12.0 volt VPP is not
required for in-system write or erase operations. However,
the A29L040A can also be programmed in standard EPROM
programmers.
The A29L040A has a second toggle bit, I/O
whether the addressed sector is being selected for erase,
and also offers the ability to program in the Erase Suspend
mode. The standard A29L040A offers access times of 70ns,
allowing high-speed microprocessors to operate without wait
states. To eliminate bus contention the device has separate
chip enable (
(
The device requires only a single 3.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
OE
Single power supply operation
- Full voltage range: 2.7 to 3.6 volt read and write
- Regulated voltage range: 3.0 to 3.6 volt read and write
Access times:
- 70 (max.)
Current:
- 4 mA typical active read current
- 20 mA typical program/erase current
- 200 nA typical CMOS standby
- 200 nA Automatic Sleep Mode current
Flexible sector architecture
- 8 uniform sectors of 64 Kbyte each
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
Embedded Erase Algorithms
0
operations for battery-powered applications
operations for compatibility with high performance 3.3
volt microprocessors
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within that
sector
- I/O
) controls.
7
while the addresses are input on A0 to A18. The
CE
(March, 2005, Version 0.0)
), write enable ( WE ) and output enable
Flash standard.
2
, to indicate
1
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
The host system can detect whether a program or erase
operation is complete by reading the I/O
I/O
been completed, the device is ready to read array data or
accept another command.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
6
Typical 100,000 program/erase cycles per sector
- Embedded Erase algorithm will automatically erase the
- Embedded Program algorithm automatically writes and
20-year data retention at 125°C
- Reliable operation for the life of the system
Compatible with JEDEC-standards
- Pinout and software compatible with single-power-
- Superior inadvertent write protection
- Provides a software method of detecting completion of
Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from,
Package options
- 32-pin DIP, PLCC, TSOP (8mm x 20mm), sTSOP
Data
(toggle) status bits. After a program or erase cycle has
entire chip or any combination of designated sectors
and verify the erased sectors
verifies bytes at specified addresses
supply Flash memory standard
program or erase operations
or program data to, a non-erasing sector, then
resumes the erase operation
(8mm x 13.4mm), sTSOP (8mm x 14mm).
512K X 8 Bit CMOS 3.0 Volt-only,
Uniform Sector Flash Memory
Polling and toggle bits
-
an
internal
A29L040A Series
AMIC Technology, Corp.
algorithm
7
that
(
Data
automatically
Polling) and