A29L040-70 AMICC [AMIC Technology], A29L040-70 Datasheet - Page 13

• Manufacturer Part Number: A29L040-70
• Description: 512K X 8 Bit CMOS 3.0 Volt-only, Uniform Sector Flash Memory
• Manufacturer: AMICC [AMIC Technology]

I/O
those sectors that have been selected for erasure. (The
system may use either
cycles.) But I/O
actively erasing or is erase-suspended. I/O
indicates whether the device is actively erasing, or is in
Erase Suspend, but cannot distinguish which sectors are
selected for erasure. Thus, both status bits are required for
Toggle Bit I on I/O
Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid after
the rising edge of the final
sequence (prior to the program or erase operation), and
during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address cause
I/O
control the read cycles.) When the operation is complete,
I/O
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O
approximately 100 s, then returns to reading array data. If
not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O
device enters the Erase Suspend mode, I/O
However, the system must also use I/O
sectors are erasing or erase-suspended. Alternatively, the
system can use I/O
Polling").
If a program address falls within a protected sector, I/O
toggles for approximately 2 s after the program command
sequence is written, then returns to reading array data.
I/O
and stops toggling once the Embedded Program algorithm
is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O
algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram. The I/O
I/O
graphical form. See also the subsection on " I/O
Bit II".
I/O
The "Toggle Bit II" on I/O
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final
sequence.
I/O
PRELIMINARY
2
6
6
6
6
2
6
stops toggling.
: Toggle Bit II
: Toggle Bit I
also toggles during the erase-suspend-program mode,
figure shows the differences between I/O
to toggle. (The system may use either
toggles when the system reads at addresses within
2
cannot distinguish whether the sector is
(June, 2003, Version 0.1)
6
7
. Refer to Figure 4 for the toggle bit
(see the subsection on " I/O
6
indicates whether an Embedded
6
2
OE
, when used with I/O
and I/O
WE
WE
or
pulse in the command
CE
2
pulse in the command
together to determine
6
2
to control the read
toggles. When the
to determine which
6
6
, by comparison,
6
stops toggling.
OE
2
toggles for
6
and I/O
, indicates
or
2
7
: Toggle
:
CE
Data
2
6
vs.
to
in
6
12
sector and mode information. Refer to Table 5 to compare
outputs for I/O
Figure 4 shows the toggle bit algorithm in flowchart form, and
the section " I/O
also the " I/O
Bit Timings figure for the toggle bit timing diagram. The I/O
vs. I/O
graphical form.
Reading Toggle Bits I/O
Refer to Figure 4 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O
toggle bit is toggling. Typically, a system would note and
store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of the
toggle bit with the first. If the toggle bit is not toggling, the
device has completed the program or erase operation. The
system can read array data on I/O
read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O
on I/O
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O
is no longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and the
system must write the reset command to return to reading
array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O
system may continue to monitor the toggle bit and I/O
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figure
4).
I/O
I/O
exceeded a specified internal pulse count limit. Under these
conditions I/O
indicates the program or erase cycle was not successfully
completed.
The I/O
program a "1 "to a location that is previously programmed to
"0." Only an erase operation can change a "0" back to a "1."
Under this condition, the device halts the operation, and
when the operation has exceeded the timing limits, I/O
produces a "1."
Under both these conditions, the system must issue the reset
command to return the device to reading array data.
7
5
5
: Exceeded Timing Limits
- I/O
indicates whether the program or erase time has
6
5
). If it is, the system should then determine again
5
figure shows the differences between I/O
failure condition may appear if the system tries to
0
at least twice in a row to determine whether a
6
5
2
: Toggle Bit I" subsection. Refer to the Toggle
produces a "1." This is a failure condition that
and I/O
2
: Toggle Bit II" explains the algorithm. See
6
.
AMIC Technology, Corp.
6
, I/O
A29L040 Series
5
2
went high. If the toggle bit
7
5
5
is high (see the section
has not gone high. The
- I/O
0
on the following
2
and I/O
6
in
2
5
5