A290011TV-90 AMICC [AMIC Technology], A290011TV-90 Datasheet - Page 13

• Manufacturer Part Number: A290011TV-90
• Description: 128K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory
• Manufacturer: AMICC [AMIC Technology]

Write Operation Status
Several bits, I/O
the A29001/A290011 to determine the status of a write
operation. Table 6 and the following subsections describe
the functions of these status bits. I/O
offer a method for determining whether a program or erase
operation is complete or in progress. These three bits are
discussed first.
I/O
The
whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.
pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device
outputs on I/O
to I/O
Erase Suspend. When the Embedded Program algorithm
is complete, the device outputs the datum programmed to
I/O
read valid status information on I/O
falls within a protected sector,
active for approximately 2µs, then the device returns to
reading array data.
During the Embedded Erase algorithm,
produces a "0" on I/O
algorithm is complete, or if the device enters the Erase
Suspend mode,
is analogous to the complement/true datum output
described for the Embedded Program algorithm: the erase
function changes all the bits in a sector to "1"; prior to this,
the device outputs the "complement," or "0." The system
must provide an address within any of the sectors selected
for erasure to read valid status information on I/O
After an erase command sequence is written, if all sectors
selected for erasing are protected,
active for approximately 100µs, then the device returns to
reading array data. If not all selected sectors are
protected, the Embedded Erase algorithm erases the
unprotected sectors, and ignores the selected sectors that
are protected.
When the system detects I/O
complement to true data, it can read valid data at I/O
I/O
change asynchronously with I/O
Enable (
(During
Characteristics" section illustrates this. Table 6 shows the
outputs for
Polling algorithm.
(December, 2004, Version 1.3)
Data
7
0
7
. The system must provide the program address to
: Data Polling
on the following read cycles. This is because I/O
Data
7
Polling is valid after the rising edge of the final
. This I/O
OE
Embedded
Polling bit, I/O
Data
) is asserted low. The
7
7
the complement of the datum programmed
2
Data
status also applies to programming during
, I/O
Polling on I/O
3
, I/O
Polling produces a "1" on I/O
Algorithms)
7
. When the Embedded Erase
7
5
, indicates to the host system
, I/O
7
6
. Figure 4 shows the
7
, and I/O
Data
has changed from the
0
7
Data
. If a program address
Data
figure
- I/O
7
, I/O
Polling on I/O
7,
Polling on I/O
6
6
Polling Timings
are provided in
and I/O
in
Data
while Output
7
the
.
Polling
2
7
7
Data
each
.This
WE
may
"AC
7
7
7
is
is
-
12
Note :
1. VA = Valid address for programming. During a sector
2. I/O
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
I/O
No
7
7
should be rechecked even if I/O
may change simultaneously with I/O
Figure 4. Data Polling Algorithm
A29001/A290011 Series
Read I/O
Read I/O
Address = VA
Address = VA
I/O
I/O
I/O
AMIC Technology, Corp.
START
7
7
FAIL
= Data ?
= Data ?
5
= 1?
7
7
-I/O
Yes
- I/O
No
No
0
0
5
Yes
= "1" because
Yes
5
.
PASS