GAL16V811111 LATTICE [Lattice Semiconductor], GAL16V811111 Datasheet - Page 6

• Manufacturer Part Number: GAL16V811111
• Description: High Performance E2CMOS PLD Generic Array Logic
• Manufacturer: LATTICE [Lattice Semiconductor]

In the Complex mode, macrocells are configured as output only
or I/O functions.
Architecture configurations available in this mode are similar to
the common 16L8 and 16P8 devices with programmable polarity
in each macrocell.
Up to six I/O's are possible in this mode. Dedicated inputs or
outputs can be implemented as subsets of the I/O function. The
two outer most macrocells (pins 12 & 19) do not have input ca-
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
COMPLEX MODE
XOR
XOR
3-70
pability. Designs requiring eight I/O's can be implemented in the
Registered mode.
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
11 are always available as data inputs into the AND array.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
Combinatorial I/O Configuration for Complex Mode
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 13 through Pin 18 are configured to this function.
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 12 and Pin 19 are configured to this function.
Specifications GAL16V8
1996 Data Book