GAL16V811111 LATTICE [Lattice Semiconductor], GAL16V811111 Datasheet - Page 15

• Manufacturer Part Number: GAL16V811111
• Description: High Performance E2CMOS PLD Generic Array Logic
• Manufacturer: LATTICE [Lattice Semiconductor]

Note: fmax with external feedback is calculated from measured
tsu and tco.
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
3-state levels are measured 0.5V from steady-state active
level.
GAL16V8B Output Load Conditions (see figure)
fmax DESCRIPTIONS
Input Pulse Levels
Input Rise and
Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
SWITCHING TEST CONDITIONS
Test Condition
A
B
C
f
Active High
Active Low
Active High
Active Low
max with External Feedback 1/(
LOGIC
ARRAY
t
su +
f
LOGIC
ARRAY
max with No Feedback
t
h
t
su
GAL16V8C
GAL16V8B
200
200
200
R
1
REGISTER
REGISTER
CLK
CLK
390
390
390
390
390
2 – 3ns 10% – 90%
1.5ns 10% – 90%
R
2
t
t
GND to 3.0V
co
See Figure
su+
1.5V
1.5V
t
co)
50pF
50pF
50pF
5pF
5pF
C
L
3-79
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
GAL16V8C Output Load Conditions (see figure)
Test Condition
A
B
C
FROM OUTPUT (O/Q)
UNDER TEST
Active High
Active Low
Active High
Active Low
*C
f
max with Internal Feedback 1/(
L
Specifications GAL16V8
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
LOGIC
ARRAY
R
2
200
200
200
t
R
cf
t
+5V
pd
1
REGISTER
CLK
R
1
200
200
200
200
200
R
2
t
C *
su+
L
1996 Data Book
TEST POINT
t
cf)
50pF
50pF
50pF
5pF
5pF
C
L