ISPLSI2128VL-100LB208 LATTICE [Lattice Semiconductor], ISPLSI2128VL-100LB208 Datasheet - Page 7

• Manufacturer Part Number: ISPLSI2128VL-100LB208
• Manufacturer: LATTICE [Lattice Semiconductor]

Derivations of
Y0,1,2
GOE 0
ispLSI 2128VL Timing Model
Ded. In
I/O Pin
Reset
(Input)
t
t
t
Note: Calculations are based upon timing specifications for the ispLSI 2128VL-150L.
su
h
co
4.0ns
3.0ns
9.0ns
=
=
=
=
=
=
=
=
=
=
=
=
Logic + Reg su - Clock (min)
(
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.4 + 1.1 + 4.0) + (1.2) - (0.4 + 1.1 + 1.2)
Clock (max) + Reg h - Logic
(
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.4 + 1.1 + 4.2) + (2.8) - (0.4 + 1.1 + 4.0)
Clock (max) + Reg co + Output
(
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.4 + 1.1 + 4.2) + (0.3) + (1.4 + 1.6)
t
t
t
I/O Delay
io +
io +
io +
#21
#20
t
I/O Cell
su,
t
t
t
grp +
grp +
grp +
t
h and
t
t
t
20ptxor) + (
ptck(max)) + (
ptck(max)) + (
t
co from the Product Term Clock
#45
#43, 44
#42
t
GRP
GRP
#22
gsu) - (
t
t
gh) - (
gco) + (
t
io +
t
io +
t
orp +
t
grp +
t
grp +
Reg 4 PT Bypass
#33, 34,
XOR Delays
t
Control
PTs
Feedback
#25, 26, 27
ob)
t
20 PT
35
ptck(min))
t
#24
20ptxor)
Comb 4 PT Bypass #23
7
OE
RE
CK
Specifications ispLSI 2128VL
GLB
GLB Reg Bypass
D
RST
GLB Reg
Delay
#28
Table 2-0042/2128VL
#29, 30,
31, 32
Q
ORP Bypass
Delay
ORP
ORP
#36
#37
#40, 41
0491/2032
#38,
39
I/O Cell
(Output)
I/O Pin