ISPLSI2128VL-100LB208 LATTICE [Lattice Semiconductor], ISPLSI2128VL-100LB208 Datasheet
ISPLSI2128VL-100LB208
Related parts for ISPLSI2128VL-100LB208
ISPLSI2128VL-100LB208 Summary of contents
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Features • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 6000 PLD Gates — 128 and 64 I/O Pin Versions, Eight Dedicated Inputs — 128 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address ...
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Functional Block Diagram Figure 1. ispLSI 2128VL Functional Block Diagram (128-I/O and 64-I/O Versions) RESET Input Bus GOE 0 GOE 1 Output Routing Pool (ORP) Output Routing Pool (ORP) Megablock I I/O 1 ...
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Absolute Maximum Ratings Supply Voltage V ................................ -0.5 to +4.05V cc Input Voltage Applied ............................. -0.5 to +4.05V Off-State Output Voltage Applied .......... -0.5 to +4.05V Storage Temperature ................................ -65 to 150 C Case Temp. with Power Applied .............. -55 ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.15V from steady-state active level. Output Load Conditions (see Figure 2) TEST CONDITION A Active ...
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External Timing Parameters 3 TEST PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay pd2 f max A 3 Clock Frequency with Internal Feedback f — 4 Clock Frequency ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...
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Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset #43, 44 Y0,1,2 GOE Derivations of su, h and co from the Product Term Clock Logic ...
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Power Consumption Power consumption in the ispLSI 2128VL device de- pends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax 200 180 160 ...
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Signal Descriptions Signal Name RESET Active Low (0) Reset pin resets all the registers in the device. GOE 0, GOE1 Global Output Enable input pins. Y0, Y1, Y2 Dedicated Clock Input – These clock inputs are connected to one of ...
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Signal Locations ...
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I/O Locations 208 176 160 Signal fpBGA TQFP PQFP I/O ...
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Signal Configuration ispLSI 2128VL 208-Ball fpBGA Signal Diagram I/O I/O I I/O I I/O I/O I ...
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Pin Configuration ispLSI 2128VL 176-Pin TQFP Pinout Diagram I/O 113 1 VCC 2 3 I/O 114 4 I/O 115 5 I/O 116 6 I/O 117 7 I/O 118 8 I/O 119 I/O 120 10 I/O 121 11 ...
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Pin Configuration ispLSI 2128VL 160-Pin PQFP Pinout Diagram 1 I/O 113 2 VCC 3 I/O 114 4 I/O 115 I/O 116 5 I/O 117 6 7 I/O 118 8 I/O 119 9 I/O 120 10 I/O 121 11 I/O 122 ...
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Signal Configuration ispLSI 2128VL 100-Ball caBGA Signal Diagram 10 9 I/O I I/O I I/O I I/O I GOE F VCC 0 TCK/ ...
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Pin Configuration ispLSI 2128VL 100-Pin TQFP Pinout Diagram RESET 11 VCC ...
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Part Number Description ispLSI 2128VL Device Family Device Number Speed f 150 = 150 MHz max f 135 = 135 MHz max f 100 = 100 MHz max ispLSI 2128VL Ordering Information FAMILY fmax (MHz) tpd (ns) 150 6.0 150 ...