ISPLSI2032VE-110LB49 LATTICE [Lattice Semiconductor], ISPLSI2032VE-110LB49 Datasheet
ISPLSI2032VE-110LB49
Related parts for ISPLSI2032VE-110LB49
ISPLSI2032VE-110LB49 Summary of contents
Page 1
Features • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 1000 PLD Gates — 32 I/O Pins, Two Dedicated Inputs — 32 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — ...
Page 2
Functional Block Diagram Figure 1. ispLSI 2032VE Functional Block Diagram GOE 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 ...
Page 3
Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +5.4V cc Input Voltage Applied ............................... -0.5 to +5.6V Off-State Output Voltage Applied ............ -0.5 to +5.6V Storage Temperature .............................. -65 to +150 C Case Temp. with Power Applied .............. -55 ...
Page 4
Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure 2) TEST ...
Page 5
External Timing Parameters 3 TEST PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay pd2 Clock Frequency with Internal Feedback max f max (Ext.) – 4 ...
Page 6
External Timing Parameters 3 TEST PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay pd2 f max A 3 Clock Frequency with Internal Feedback f – 4 Clock Frequency ...
Page 7
Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...
Page 8
Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t 22 GRP Delay grp GLB t 4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial Product ...
Page 9
Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset Y0,1,2 GOE Derivations of su, h and co from the Product Term Clock Logic + Reg ...
Page 10
Power Consumption Power consumption in the ispLSI 2032VE device de- pends on two primary factors: the speed at which the device is operating and the number of product terms Figure 3. Typical Device Power Consumption vs fmax 150 125 100 ...
Page 11
Signal Descriptions Signal Name GOE 0 Global Output Enable Pin Y0 Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. RESET/Y1 This pin performs two functions: (1) Dedicated ...
Page 12
Pin Configuration ispLSI 2032VE 44-Pin TQFP Pinout Diagram I/O 28 I/O 29 I VCC BSCAN TDI/IN 0 I/O 0 I pins are not to be connected to any active signals, VCC ...
Page 13
Pin Configuration ispLSI 2032VE 48-Pin TQFP Pinout Diagram I/O 28 I/O 29 I/O 30 I/O 31 VCC BSCAN 1 TDI/IN 0 I/O 0 I Pins have dual function capability pins are not ...
Page 14
Part Number Description ispLSI 2032VE – XXX Device Family Device Number 2032VE Speed f 225 = 225 MHz max f 180 = 180 MHz max f 135 = 135 MHz max f 110 = 110 MHz max ispLSI 2032VE Ordering ...