ISPLSI2032V-100LT44 Lattice Semiconductor Corp., ISPLSI2032V-100LT44 Datasheet

ISPLSI2032V-100LT44

Manufacturer Part Number

ISPLSI2032V-100LT44

Description

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.ISPLSI2032V-80LT44.pdf (12 pages)

Specifications of ISPLSI2032V-100LT44

Package

QFP

Date_code

09+

Current page: 1 of 12
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• HIGH DENSITY PROGRAMMABLE LOGIC

• 3.3V LOW VOLTAGE 2032 ARCHITECTURE

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

2032v_10

Features

— 1000 PLD Gates

— 32 I/O Pins, Two Dedicated Inputs

— 32 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic

— Interfaces With Standard 5V TTL Devices

— 60 mA Typical Active Current

— Fuse Map Compatible with 5V ispLSI 2032

—

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— 3.3V In-System Programmability Using Boundary

— Open-Drain Output Option for Flexible Bus Interface

— Increased Manufacturing Yields, Reduced Time-to-

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

— PC and UNIX Platforms

Machines, Address Decoders, etc.

Scan Test Access Port (TAP)

Capability, Allowing Easy Implementation of

Wired-OR or Bus Arbitration Logic

Market and Improved Product Quality

Tools, Timing Simulator and ispANALYZER™

Interconnectivity

max = 100 MHz Maximum Operating Frequency

pd = 7.5 ns Propagation Delay

CMOS

TECHNOLOGY

The ispLSI 2032V is a High Density Programmable Logic

Device that can be used in both 3.3V and 5V systems.

The device contains 32 Registers, 32 Universal I/O pins,

two Dedicated Input Pins, three Dedicated Clock Input

Pins, one dedicated Global OE input pin and a Global

Routing Pool (GRP). The GRP provides complete

interconnectivity between all of these elements. The

ispLSI 2032V features in-system programmability through

the Boundary Scan Test Access Port (TAP). The ispLSI

2032V offers non-volatile reprogrammability of the logic,

as well as the interconnect to provide truly reconfigurable

systems.

The basic unit of logic on the ispLSI 2032V device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. A7 (see Figure 1). There are a total of eight GLBs in the

ispLSI 2032V device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

Functional Block Diagram

Description

3.3V High Density Programmable Logic

GLB

ispLSI

Global Routing Pool

Logic

Array

(GRP)

D Q

September 2000

2032V

0139Bisp/2000

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