HT82A821R_07 HOLTEK [Holtek Semiconductor Inc], HT82A821R_07 Datasheet - Page 9

• Manufacturer Part Number: HT82A821R_07
• Description: USB Audio MCU
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be
set to allow interrupt nesting. If the stack is full, the inter-
rupt request will not be acknowledged, even if the re-
lated interrupt is enabled, until the SP is decremented. If
immediate service is desired, the stack must be pre-
vented from becoming full.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at a specified location in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register or status
register (STATUS) are altered by the interrupt service
program which corrupts the desired control sequence,
the contents should be saved in advance.
The USB interrupts are triggered by the following USB
events and the related interrupt request flag (USBF; bit
4 of the INTC0) will be set.
When the interrupt is enabled, the stack is not full and
the external interrupt is active, a subroutine call to loca-
tion 04H will occur. The interrupt request flag (USBF)
and EMI bits will be cleared to disable other interrupts.
When PC Host access the FIFO of the HT82A821R, the
corresponding request bit of USR is set, and a USB in-
terrupt is triggered. So user can easy to decide which
FIFO is accessed. When the interrupt has been served,
the corresponding bit should be cleared by firmware.
When HT82A821R receive a USB Suspend signal from
Host PC, the suspend line (bit0 of USC) of the
HT82A821R is set and a USB interrupt is also triggered.
When the HT82A821R receives a Resume signal from
the Host PC, the resume line (bit3 of the USC) of the
HT82A821R are set and a USB interrupt is triggered.
Also when HT82A821R receive a Resume signal from
Host PC, the resume line (bit3 of USC) of HT82A821R is
Rev. 1.10
Access of the corresponding USB FIFO from PC
The USB suspend signal from PC
The USB resume signal from PC
USB Reset signal
Bit No.
0
1
2
3
4
5
6
7
Label
USBF
ET0I
ET1I
EMI
T0F
T1F
EUI
Controls the master (global) interrupt (1=enable; 0=disable)
Controls the USB interrupt (1=enable; 0= disable)
Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)
Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable)
USB interrupt request flag (1=active; 0=inactive)
Internal Timer/Event Counter 0 request flag (1:active; 0:inactive)
Internal Timer/Event Counter 1 request flag (1:active; 0:inactive)
Unused bit, read as 0
INTC0 (0BH) Register
9
set and a USB interrupt is triggered.
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (bit 5 of INTC0), caused by a timer 0 overflow.
When the interrupt is enabled, the stack is not full and
the T0F bit is set, a subroutine call to location 08H will
occur. The related interrupt request flag (T0F) will be re-
set and the EMI bit cleared to disable further interrupts.
The internal Timer/Even Counter 1 interrupt is initialized
by setting the Timer/Event Counter 1 interrupt request
flag (bit 6 of INTC0), caused by a timer 1 overflow. When
the interrupt is enabled, the stack is not full and the T1F
is set, a subroutine call to location 0CH will occur. The
related interrupt request flag (T1F) will be reset and the
EMI bit cleared to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledge signals are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, RET or RETI
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
It is recommended that a program does not use the
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left and enabling the interrupt is not well
controlled, the original control sequence will be dam-
aged once the CALL operates in the interrupt subrou-
tine.
CALL subroutine within the interrupt subroutine. Inter-
No.
a
b
c
Function
USB interrupt
Timer/Event Counter 0 overflow
Timer/Event Counter 1 overflow
Interrupt Source
HT82A821R
Priority Vector
June 29, 2007
1
2
3
0CH
04H
08H