ADUM5401_VB AD [Analog Devices], ADUM5401_VB Datasheet - Page 20

• Manufacturer Part Number: ADUM5401_VB
• Description: Quad-Channel, 2.5 kV Isolators with Integrated DC-to-DC Converter
• Manufacturer: AD [Analog Devices]

ADuM5401/ADuM5402/ADuM5403/ADuM5404
APPLICATIONS INFORMATION
The dc-to-dc converter section of the ADuM5401/ADuM5402/
ADuM5403/ADuM5404
most switching power supplies. It has a secondary side controller
architecture with isolated pulse-width modulation (PWM)
feedback. V
switches current into a chip-scale air core transformer. Power
transferred to the secondary side is rectified and regulated to
either 3.3 V or 5 V. The secondary (V
the output by creating a PWM control signal that is sent to the
primary (V
PWM modulates the oscillator circuit to control the power being
sent to the secondary side. Feedback allows for significantly higher
power and efficiency.
The
undervoltage lockout (UVLO) with hysteresis on the V
input. This feature ensures that the converter does not enter
oscillation due to noisy input power or slow power-on ramp rates.
PCB LAYOUT
The
isolators with 0.5 W isoPower integrated dc-to-dc converter
require no external interface circuitry for the logic interfaces.
Power supply bypassing is required at the input and output
supply pins (see Figure 25). Note that low ESR bypass capacitors
are required between Pin 1 and Pin 2 and between Pin 15 and
Pin 16, as close to the chip pads as possible.
The power supply section of the ADuM5401/ADuM5402/
ADuM5403/ADuM5404
to pass power efficiently through its chip scale transformers. In
addition, the normal operation of the data section of the iCoupler
introduces switching transients on the power supply pins. Bypass
capacitors are required for several operating frequencies. Noise
suppression requires a low inductance, high frequency capacitor;
ripple suppression and proper regulation require a large value
capacitor. These are most conveniently connected between Pin 1
and Pin 2 for V
To suppress noise and reduce ripple, a parallel combination of
at least two capacitors is required. The recommended capacitor
values are 0.1 μF and 10 μF for V
capacitor must have a low ESR; for example, use of a ceramic
capacitor is advised.
The total lead length between the ends of the low ESR capacitor
and the input power supply pin must not exceed 2 mm. Installing
the bypass capacitor with traces more than 2 mm in length may
result in data corruption. Consider bypassing between Pin 1 and
Pin 8 and between Pin 9 and Pin 16 unless both common
ground pins are connected together close to the package.
ADuM5401/ADuM5402/ADuM5403/ADuM5404
ADuM5401/ADuM5402/ADuM5403/ADuM5404
DD1
DD1
) side by a dedicated iCoupler data channel. The
power is supplied to an oscillating circuit that
DD1
and between Pin 15 and Pin 16 for V
works on principles that are common to
uses a 180 MHz oscillator frequency
DD1
ISO
and V
) side controller regulates
ISO
. The smaller
implement
DD1
digital
ISO
power
.
Rev. B | Page 20 of 28
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout such that any coupling that
does occur affects all pins equally on a given component side.
Failure to ensure this can cause voltage differentials between
pins exceeding the absolute maximum ratings for the device
as specified in Table 19, thereby leading to latch-up and/or
permanent damage.
The
devices that dissipates approximately 1 W of power when fully
loaded and running at maximum speed. Because it is not possible
to apply a heat sink to an isolation device, the devices primarily
depend on heat dissipation into the PCB through the GND
pins. If the devices are used at high ambient temperatures, provide
a thermal path from the GND pins to the PCB ground plane.
The board layout in Figure 25 shows enlarged pads for Pin 8 and
Pin 9. Large diameter vias should be implemented from the pad to
the ground, and power planes should be used to reduce inductance.
Multiple vias should be implemented from the pad to the ground
plane to significantly reduce the temperature inside the chip.
The dimensions of the expanded pads are at the discretion of
the designer and depend on the available board space.
THERMAL ANALYSIS
The
consist of four internal die attached to a split lead frame with two
die attach paddles. For the purposes of thermal analysis, the die
is treated as a thermal unit, with the highest junction temperature
reflected in the θ
measurements taken with the parts mounted on a JEDEC standard,
4-layer board with fine width traces and still air. Under normal
operating conditions, the ADuM5401/ADuM5402/ADuM5403/
ADuM5404
range without derating the output current. However, following the
recommendations in the PCB Layout section decreases thermal
resistance to the PCB, allowing increased thermal margins in high
ambient temperatures.
V
V
V
V
ADuM5401/ADuM5402/ADuM5403/ADuM5404
BYPASS < 2mm
ADuM5401/ADuM5402/ADuM5403/ADuM5404
RC
IB
IC
ID
IA
GND
GND
V
/V
/V
/V
/V
OUT
DD1
OB
OC
OD
OA
1
1
devices operate at full load across the full temperature
Figure 25. Recommended PCB Layout
JA
from Table 14. The value of θ
Data Sheet
JA
is based on
V
GND
V
V
V
V
V
GND
ISO
OA
OB
OC
OD
SEL
are power
/V
/V
/V
/V
parts
ISO
ISO
IA
IB
IC
ID